XC2V4000 Datasheet, PDF (206/311 Pages) Xilinx, Inc – Summary of Features

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Virtex™-II Platform FPGAs: Pinout Information
FF1152 Flip-Chip Fine-Pitch BGA Package
As shown in Table 12, XC2V3000, XC2V4000, XC2V6000, and XC2V8000 Virtex-II devices are available in the FF1152
flip-chip fine-pitch BGA package. Pins in each of these devices are the same, except for the pin differences in the XC2V3000
device shown in the No Connect column. Following this table are the FF1152 Flip-Chip Fine-Pitch BGA Package
Specifications (1.00mm pitch).
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
Pin Description
Pin Number
0
IO_L01N_0
D29
0
IO_L01P_0
C29
0
IO_L02N_0
H26
0
IO_L02P_0
G26
0
IO_L03N_0/VRP_0
E28
0
IO_L03P_0/VRN_0
E27
0
IO_L04N_0/VREF_0
F25
0
IO_L04P_0
F26
0
IO_L05N_0
H25
0
IO_L05P_0
H24
0
IO_L06N_0
E26
0
IO_L06P_0
F27
0
IO_L19N_0
B32
0
IO_L19P_0
C33
0
IO_L20N_0
J24
0
IO_L20P_0
J23
0
IO_L21N_0
C27
0
IO_L21P_0/VREF_0
C28
0
IO_L22N_0
B30
0
IO_L22P_0
B31
0
IO_L23N_0
K23
0
IO_L23P_0
K22
0
IO_L24N_0
C26
0
IO_L24P_0
D27
0
IO_L25N_0
A30
0
IO_L25P_0
A31
0
IO_L26N_0
G24
0
IO_L26P_0
G25
0
IO_L27N_0
E25
0
IO_L27P_0/VREF_0
E24
0
IO_L28N_0
D25
No Connect in the XC2V3000
DS031-4 (v2.0) August 1, 2003
Product Specification
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