XC2V4000 Datasheet, PDF (10/311 Pages) Xilinx, Inc – Summary of Features

R
Virtex™-II Platform FPGAs: Detailed Description
Table 2: Supported Differential Signal I/O Standards
I/O Standard
LVPECL_33
Output
V_CCO
3.3
Input
V_CCO
N/A
Input
V_REF
N/A
Output
V_OD
490 mV to 1.22V
LDT_25
2.5
N/A
N/A
0.430 - 0.670
LVDS_33
3.3
N/A
N/A
0.250 - 0.400
LVDS_25
2.5
N/A
N/A
0.250 - 0.400
LVDSEXT_33 3.3
N/A
N/A
0.330 - 0.700
LVDSEXT_25 2.5
N/A
N/A
0.330 - 0.700
BLVDS_25
2.5
N/A
N/A
0.250 - 0.450
ULVDS_25
2.5
N/A
N/A
0.430 - 0.670
All of the user IOBs have fixed-clamp diodes to VCCO and
to ground. As outputs, these IOBs are not compatible or
compliant with 5V I/O standards. As inputs, these IOBs are
not normally 5V tolerant, but can be used with 5V I/O stan-
dards when external current-limiting resistors are used. For
more details, see the “5V Tolerant I/Os“ Tech Topic at
www.xilinx.com.
Table 3 lists supported I/O standards with Digitally Con-
trolled Impedance. See Digitally Controlled Impedance
(DCI), page 8.
Table 3: Supported DCI I/O Standards
I/O
Standard
LVDCI_33⁽¹⁾
LVDCI_DV2_33⁽¹⁾
LVDCI_25⁽¹⁾
LVDCI_DV2_25⁽¹⁾
LVDCI_18⁽¹⁾
LVDCI_DV2_18⁽¹⁾
LVDCI_15⁽¹⁾
LVDCI_DV2_15⁽¹⁾
Output
V_CCO
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
Input
V_CCO
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
Input
V_REF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Termination
Type
Series
Series
Series
Series
Series
Series
Series
Series
GTL_DCI
1.2
1.2
0.8
Single
GTLP_DCI
1.5
1.5
1.0
Single
HSTL_I_DCI
1.5
1.5 0.75
Split
HSTL_II_DCI
1.5
1.5 0.75
Split
HSTL_III_DCI
1.5
1.5
0.9
Single
HSTL_IV_DCI
1.5
1.5
0.9
Single
HSTL_I_DCI_18
1.8
1.8
0.9
Split
HSTL_II_DCI_18 1.8
1.8
0.9
Split
HSTL_III_DCI_18 1.8
1.8 1.08
Single
HSTL_IV_DCI_18 1.8
SSTL2_I_DCI⁽²⁾
2.5
SSTL2_II_DCI ⁽²⁾
2.5
SSTL3_I_DCI⁽²⁾
3.3
SSTL3_II_DCI ⁽²⁾
3.3
1.8 1.08
2.5 1.25
2.5 1.25
3.3
1.5
3.3
1.5
Single
Split
Split
Split
Split
Notes:
1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
impedance buffers, matching the reference resistors or half
of the reference resistors.
2. These are SSTL compatible.
Logic Resources
IOB blocks include six storage elements, as shown in
Figure 2.
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in Figure 3. There are two input, output,
and 3-state data signals, each being alternately clocked out.
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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