XC2V4000 Datasheet, PDF (36/311 Pages) Xilinx, Inc – Summary of Features

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Virtex™-II Platform FPGAs: Detailed Description
Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in Figure 38.
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
can also be driven by local interconnects. The DCM has
clock output(s) that can be connected to global clock buffer
inputs, as shown in Figure 39.
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM blocks.
Eight global clocks can be used in each quadrant of the
Virtex-II device. Designers should consider the clock distri-
bution detail of the device prior to pin-locking and floorplan-
ning (see the Virtex-II User Guide).
8 clock pads
Virtex-II
Device
8 clock pads
Clock
Pad
I
Clock
Buffer
0
Clock Distribution
Clock
Pad
CLKIN
DCM
CLKOUT
I
Clock
Buffer
DS031_42_101000
Figure 38: Virtex-II Clock Pads
Each global clock buffer can either be driven by the clock
pad to distribute a clock directly to the device, or driven by
the Digital Clock Manager (DCM), discussed in Digital
Clock Manager (DCM), page 30. Each global clock buffer
0
Clock Distribution
DS031_43_101000
Figure 39: Virtex-II Clock Distribution Configurations
Figure 40 shows clock distribution in Virtex-II devices.
8 BUFGMUX
NW
NW ^{8 BUFGMUX} NE
8
8
NE
8 max
16 Clocks
16 Clocks
8
SW _{8 BUFGMUX} SE
SW
8
SE
8 BUFGMUX
Figure 40: Virtex-II Clock Distribution
DS031_45_120200
DS031-2 (v3.0) August 1, 2003
Product Specification
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