XC2V4000 Datasheet, PDF (68/311 Pages) Xilinx, Inc – Summary of Features

R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics
Table 21: CLB Distributed RAM Switching Characteristics
Description
Symbol
Sequential Delays
Clock CLK to X/Y outputs (WE active) in 16 x 1 mode
Clock CLK to X/Y outputs (WE active) in 32 x 1 mode
Clock CLK to F5 output
Setup and Hold Times Before/After Clock CLK
T_SHCKO16
T_SHCKO32
T_SHCKOF5
BX/BY data inputs (DIN)
F/G address inputs
SR input (WS)
Clock CLK
T_DS/T_DH
T_AS/T_AH
T_WES/T_WEH
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write cycle time
T_WPH
T_WPL
T_WC
Speed Grade
–6
–5
–4
1.63
1.79
2.05
1.97
2.17
2.49
1.77
1.94
2.23
0.53/–0.09
0.40/ 0.00
0.42/–0.01
0.58/–0.10
0.44/ 0.00
0.46/–0.01
0.67/–0.11
0.50/ 0.00
0.53/–0.01
0.57
0.63
0.72
0.57
0.63
0.72
1.14
1.25
1.44
Units
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
CLB Shift Register Switching Characteristics
Table 22: CLB Shift Register Switching Characteristics
Description
Sequential Delays
Clock CLK to X/Y outputs
Clock CLK to X/Y outputs
Clock CLK to XB output via MC15 LUT output
Clock CLK to YB output via MC15 LUT output
Clock CLK to Shiftout
Clock CLK to F5 output
Setup and Hold Times Before/After Clock CLK
BX/BY data inputs (DIN)
SR input (WS)
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Symbol
T_REG
T_REG32
T_REGXB
T_REGYB
T_CKSH
T_REGF5
T_SRLDS/T_SRLDH
T_WSS/T_WSH
T_SRPH
T_SRPL
Speed Grade
–6
–5
–4
Units
2.31
2.54
2.92
ns, Max
2.65
2.92
3.35
ns, Max
2.23
2.46
2.82
ns, Max
2.18
2.40
2.75
ns, Max
1.92
2.11
2.43
ns, Max
2.45
2.69
3.09
ns, Max
0.53/–0.07
0.19/–0.06
0.58/–0.08
0.21/–0.07
0.67/–0.09
0.24/–0.08
ns, Min
ns, Min
0.57
0.63
0.72
ns, Min
0.57
0.63
0.72
ns, Min
DS031-3 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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