XC2V4000 Datasheet, PDF (63/311 Pages) Xilinx, Inc – Summary of Features

R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued)
Speed Grade
Description
Symbol
Standard
–6
–5
–4
T_{OSSTL2_I}
T_{OSSTL2_II}
T_{OSSTL3_I}
T_{OSSTL3_II}
T_OAGP
T_{OLVCMOS33_S2}
T_{OLVCMOS33_S4}
T_{OLVCMOS33_S6}
T_{OLVCMOS33_S8}
T_{OLVCMOS33_S12}
T_{OLVCMOS33_S16}
T_{OLVCMOS33_S24}
T_{OLVCMOS33_F2}
T_{OLVCMOS33_F4}
T_{OLVCMOS33_F6}
T_{OLVCMOS33_F8}
T_{OLVCMOS33_F12}
T_{OLVCMOS33_F16}
T_{OLVCMOS33_F24}
T_{OLVCMOS25_S2}
T_{OLVCMOS25_S4}
T_{OLVCMOS25_S6}
T_{OLVCMOS25_S8}
T_{OLVCMOS25_S12}
T_{OLVCMOS25_S16}
T_{OLVCMOS25_S24}
T_{OLVCMOS25_F2}
T_{OLVCMOS25_F4}
T_{OLVCMOS25_F6}
T_{OLVCMOS25_F8}
T_{OLVCMOS25_F12}
T_{OLVCMOS25_F16}
T_{OLVCMOS25_F24}
T_{OLVCMOS18_S2}
T_{OLVCMOS18_S4}
T_{OLVCMOS18_S6}
T_{OLVCMOS18_S8}
T_{OLVCMOS18_S12}
T_{OLVCMOS18_S16}
T_{OLVCMOS18_F2}
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
AGP
LVCMOS33, Slow, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVCMOS33, Fast, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVCMOS25, Slow, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVCMOS25, Fast, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVCMOS18, Slow, 2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
LVCMOS18, Fast, 2 mA
0.21
–0.15
0.29
–0.05
–0.27
7.67
4.37
3.34
2.29
1.91
1.24
1.18
5.82
2.48
1.28
0.48
0.27
–0.14
–0.21
9.11
5.00
4.53
3.86
2.84
2.36
2.00
4.06
1.15
0.72
0.33
0.02
–0.18
–0.35
15.62
10.20
7.52
6.87
5.54
5.31
5.55
0.22
–0.16
0.30
–0.05
–0.28
7.91
4.50
3.44
2.36
1.97
1.27
1.22
6.00
2.55
1.31
0.49
0.28
–0.14
–0.21
9.39
5.16
4.67
3.98
2.93
2.43
2.06
4.18
1.18
0.74
0.34
0.02
–0.19
–0.36
16.10
10.51
7.75
7.08
5.71
5.47
5.72
0.24
–0.18
0.33
–0.05
–0.31
8.70
4.95
3.78
2.60
2.16
1.40
1.34
6.60
2.81
1.45
0.54
0.31
–0.15
–0.23
10.33
5.67
5.13
4.38
3.22
2.67
2.27
4.60
1.30
0.81
0.37
0.03
–0.21
–0.40
17.71
11.57
8.53
7.78
6.28
6.02
6.30
Units
ns
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ns
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ns
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ns
ns
ns
ns
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ns
ns
ns
DS031-3 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 3 of 4
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