XC2V4000 Datasheet, PDF (32/311 Pages) Xilinx, Inc – Summary of Features

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Virtex™-II Platform FPGAs: Detailed Description
2. “READ_FIRST”
The “READ_FIRST” option is a read-before-write mode.
The same clock edge that writes data input (DI) into the memory also transfers the prior content of the memory cell
addressed into the data output registers DO, as shown in Figure 32.
Data_in
Internal
DI _Memory
DO
Prior stored data
CLK
WE
Data_in
Address
RAM Contents
Data_out
New
aa
Old
New
Old
Figure 32: READ_FIRST Mode
DS031_13_102000
3. “NO_CHANGE”
The “NO_CHANGE” option maintains the content of the output registers, regardless of the write operation. The clock edge
during the write mode has no effect on the content of the data output register DO. When the port is configured as
“NO_CHANGE”, only a read operation loads a new value in the output register DO, as shown in Figure 33.
Data_in
Internal
DI _Memory
DO
No change during write
CLK
WE
Data_in
Address
RAM Contents
Data_out
New
aa
Old
New
Last Read Cycle Content (no change)
Figure 33: NO_CHANGE Mode
DS031_12_102000
DS031-2 (v3.0) August 1, 2003
Product Specification
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