XC2V4000 Datasheet, PDF (59/311 Pages) Xilinx, Inc – Summary of Features

R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
IOB Input Switching Characteristics Standard Adjustments
Table 15: IOB Input Switching Characteristics Standard Adjustments
Description
Data Input Delay Adjustments
Standard-specific data input delay
adjustments
Symbol
Standard
T_ILVTTL
T_ILVCMOS33
T_ILVCMOS25
T_ILVCMOS18
T_ILVCMOS15
T_{ILVDS_25}
T_{ILVDS_33}
T_{ILVPECL_33}
T_{IPCI33_3}
T_{IPCI66_3}
T_IPCIX
T_IGTL
T_IGTLP
T_{IHSTL_I}
T_{IHSTL_II}
T_{IHSTL_III}
T_{IHSTL_IV}
T_{IHSTL_I_18}
T_{IHSTL_II_18}
T_{IHSTL_III_18}
T_{IHSTL_IV_18}
T_{ISSTL2_I}
T_{ISSTL2_II}
T_{ISSTL3_I}
T_{ISSTL3_II}
T_IAGP
T_{ILVDCI_33}
T_{ILVDCI_25}
T_{ILVDCI_18}
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVDS_25
LVDS_33
LVPECL
PCI, 33 MHz, 3.3 V
PCI, 66 MHz, 3.3 V
PCI–X, 133 MHz, 3.3 V
GTL
GTLP
HSTL I
HSTL II
HSTL III
HSTL IV
HSTL I_18
HSTL II_18
HSTL III_18
HSTL IV_18
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
AGP
LVDCI_33
LVDCI_25
LVDCI_18
Speed Grade
–6
–5
–4
0.00
0.00
0.00
0.00
0.00
0.00
0.11
0.11
0.12
0.42
0.43
0.49
0.98
1.00
1.15
0.60
0.60
0.69
0.60
0.60
0.69
0.60
0.60
0.69
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.35
0.35
0.40
0.35
0.35
0.40
0.35
0.35
0.40
0.00
0.00
0.00
0.11
0.11
0.12
0.42
0.43
0.49
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS031-3 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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