XC2V4000 Datasheet, PDF (12/311 Pages) Xilinx, Inc – Summary of Features

R
Virtex™-II Platform FPGAs: Detailed Description
The synchronous reset overrides a set, and an asynchro-
nous clear overrides a preset.
(O/T) 1
(O/T) CE
(O/T) CLK1
Shared ^SR
by all
registers REV
(O/T) CLK2
(O/T) 2
FF
LATCH
D1 ^Q1
Attribute INIT1
INIT0
SRHIGH
SRLOW
CE
CK1
SR REV
FF1
DDR MUX
FF2
(OQ or TQ)
FF
LATCH
D2 Q2
CE
CK2
SR REV
Attribute _INIT1
INIT0
SRHIGH
SRLOW
Reset Type
SYNC
ASYNC
Figure 4: Register / Latch Configuration in an IOB Block
DS031_25_110300
Input/Output Individual Options
Each device pad has optional pull-up and pull-down in all
SelectI/O-Ultra configurations. Each device pad has
optional weak-keeper in LVTTL, LVCMOS, and PCI
SelectI/O-Ultra configurations, as illustrated in Figure 5.
Values of the optional pull-up and pull-down resistors are in
the range 10 - 60 KΩ, which is the specification for V_CCO
when operating at 3.3V (from 3.0 to 3.6V only). The clamp
diode is always present, even when power is not.
OBUF
VCCO
Clamp
Diode
Program Current
VCCO
10-60KΩ
Weak
Keeper
Program
Delay
VCCO
10-60KΩ
IBUF
Figure 5: LVTTL, LVCMOS or PCI SelectI/O-Ultra Standards
PAD
VCCAUX = 3.3V
VCCINT = 1.5V
DS031_23_011601
DS031-2 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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