XC2V4000 Datasheet, PDF (60/311 Pages) Xilinx, Inc – Summary of Features

R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued)
Speed Grade
Description
Symbol
Standard
–6
–5
–4
T_{ILVDCI_15}
LVDCI_15
T_{ILVDCI_DV2_33}
LVDCI_DV2_33
T_{ILVDCI_DV2_25}
LVDCI_DV2_25
T_{ILVDCI_DV2_18}
LVDCI_DV2_18
T_{ILVDCI_DV2_15}
LVDCI_DV2_15
T_{IGTL_DCI}
GTL_DCI
T_{IGTLP_DCI}
GTLP_DCI
T_{IHSTL_I_DCI}
HSTL_I_DCI
T_{IHSTL_II_DCI}
HSTL_II_DCI
T_{IHSTL_III_DCI}
HSTL_III_DCI
T_{IHSTL_IV_DCI}
HSTL_IV_DCI
T_{IHSTL_I_DCI_18}
HSTL_I_DCI_18
T_{IHSTL_II_DCI_18}
HSTL_II_DCI_18
T_{IHSTL_III_DCI_18}
HSTL_III_DCI_18
T_{IHSTL_IV_DCI_18}
HSTL_IV_DCI_18
T_{ISSTL2_I_DCI}
SSTL2_I_DCI
T_{ISSTL2_II_DCI}
SSTL2_II_DCI
T_{ISSTL3_I_DCI}
SSTL3_I_DCI
T_{ISSTL3_II_DCI}
SSTL3_II_DCI
T_{ILDT_25}
LDT_25
T_{IULVDS_25}
ULVDS_25
Notes:
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 18.
0.98
1.00
1.14
0.00
0.00
0.00
0.11
0.11
0.12
0.42
0.43
0.49
0.98
1.00
1.14
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.42
0.42
0.48
0.35
0.35
0.40
0.35
0.35
0.40
0.48
0.49
0.56
0.48
0.49
0.56
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS031-3 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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