DS606 Datasheet, PDF (9/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Protocol and Electrical Characteristics of IIC.
To understand and utilize the register based software interface in the XPS IIC module it is helpful to have a basic
understanding of the IIC protocol, and the electrical characteristics of the bus. For more details and timing
diagrams, see the Philips I²C specification.
Electrical Issues
An IIC bus consists of two wires named serial data (SDA) and serial clock (SCL), which carry information between
the devices connected to the bus. The 400 pF maximum signal load capacitance limits the maximum number of
devices connectable to the same bus.
Both SDA and SCL transport data bidirectionally between connected devices using wired-and electrical
connectivity. To implement the wired-and each device utilizes an open-collector |open-drain output that only sinks
current to ground to pull the signal to logic-0. Electrically that means it may not drive a logic-1 on to either bus signal
but may only release or float the output. When no device asserts a logic-0 onto the bus, external pull-up devices
(typically resistors) bring the signal state high. This method creates a source of confusion since no device may
actually set the state of SCL or SDA to its high (logic-1) state.
The system designer must pay careful attention to the value of these pull-ups to guarantee that the implementation
(consisting of the XPS IIC pcore, the Xilinx FPGA, and other devices on the bus) does not violate the IIC timing
parameters. Selecting the value of pull-up resistors for a particular application is beyond the scope of the XPS IIC
and this document.
The user should consider utilizing the small, additional amount of logic necessary for filtering of SCL and SDA by
specifying non-zero values for the parameters C_SCL_INERTIAL_DELAY and C_SDA_INERTIAL_DELAY.
Reliability of the system may increase substantially.
When all devices on the bus release their drivers and both SDA and SCL are high for a specified period of time the
bus is considered to be in the bus free state.
Protocol for Address and Data Transfer
Each device on the bus has a unique seven-bit or ten-bit address, operate both as a transmitter and receiver and
additionally may be a a master or slave. Master device initiate data transfer on the bus and generate the clock signal
for that transfer. Slaves respond to the address clocked into them by the master and either accept ("write") data from
or provide ("read") data to the master
The IIC protocol defines an arbitration procedure that insures that if more than one Master simultaneously tries to
control the bus, only one is allowed to do so and the message is not corrupted. The arbitration and clock
synchronization procedures defined in the Philips IIC specification are supported by the XPS IIC Bus Interface
module.
Data transfers on the IIC bus are initiated with a START condition and are terminated with a STOP condition. After
reaching the bus free state a master may signal a START defined by a high-to-low transition on SDA while SCL is
high. Likewise, the master signals a STOP by a low-to-high transition on the SDA line while SCL is high. Between
the START and STOP conditions of the bus, data on the SDA signal must be stable during the high period of the SCL
signal and must meet any required setup and hold times during the low period of the SCL signal.
DS606 June 22, 2011
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Product Specification