DS606 Datasheet, PDF (10/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Figure 2 illustrates how the definitions of: (a) the bus free state, and (b) the times when SDA and SCL may change
relative to each other, ensure that the START and STOP conditions are not confused as data.
Figure Top x-ref 2
SDA
MSB
SCL
S
1
2
3
START
CONDIT ION
7
8
9
P
ACK
S TO P
CONDITION
Figure 2: Data Transfer on the IIC Bus
Each transfer on the IIC bus consists of nine clock pulses on SCL to move eight bits of data and one acknowledge bit.
Master and slave transmitter send data with the most significant bit first (MSB).
After providing data for the eight clock period, the (master | slave) transmitter releases the SDA line during the
acknowledgement clock period to permit the receiver to transfer a 1-bit acknowledgment.
If a slave-receiver issues a not-acknowledge (by releasing the SDA signal during the acknowledgement clock
period) this indicates that the slave-receiver was unable to accept the prior 8-bits transferred (consisting of address
or data bits.) Note that after a byte of data is transferred the slave (receiver | transmitter) has the unique capability
to throttle the transfer by keeping the SCL line in its low state by actively pulling the SCL line low for an arbitrary
period of time. This ability allows it time to determine internally what value it should place on the SDA line for the
acknowledgement.
Note:
1. The wired-and nature of the bus signals and each device’s pull-low or release output capability permit
bi-directional data transfer
2. This means the master and slaves in the system cooperatively determine the speed of data transfers. The
masters set the maximum speed and the slaves (and/or masters) can arbitrarily slow it down as needed. It also
means, since the master may only release the SCL line that it must check to see that SDA in fact went high before
proceeding with the next clock period.
If the master-receiver signals a not-acknowledge, this indicates to the slave-transmitter that this byte was the last
byte of the transfer.
Standard communication on the bus between a Master and a Slave is composed of four parts: START, Slave address,
Data transfer, and STOP. The IIC protocol defines a transfer format for both 7-bit and 10-bit addressing.
A seven bit address is initiated as follows. After the START condition, a Slave address is sent. This address is seven
bits long followed by an eighth-bit which is the read/write bit. A High indicates a request for data (read) and a Low
indicates a data transmission (write).
Only the Slave with the calling address that matches the address transmitted by the Master (that won arbitration)
responds by sending back an acknowledge bit by pulling the SDA line Low on the ninth clock.
For 10-bit addressing, two bytes are transferred to set the 10-bit address. The transfer of the first byte contains the
following bit definition. The first five bits (bits 7:3) notify the slave that this is a 10-bit transfer followed by the next
two bits (bits 2:1), which set the slave address bits 9:8, and the LSB bit (bit 8) is the R/W bit. The second byte
transferred sets bits 7:0 of the slave address.
DS606 June 22, 2011
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