DS606 Datasheet, PDF (26/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
2. Transmit the 7 bit address and R/W bit contained in the Tx_FIFO
3. Check the least significant bit contained with the 7 bit address to determine if this is a read or write operation
on the IIC bus
4. Get the next byte in the Tx_FIFO
5. If a read access is occurring on the IIC bus, use this value as a receive byte counter. When this counter reaches
zero, Control Register (CR) TXAK is forced High. This causes a not-acknowledge to be generated during
reception of the last byte and will signal the IIC slave device to stop transmitting read data.
6. If a write access is occurring, the contents of the Tx_FIFO are sent out on the SDA bus.
Stop Sequence:
In order for the XPS IIC controller to release the IIC bus, by clearing the MSMS in the control register, bit 22 must be
set in the Tx_FIFO with the last byte to be sent for a write access. For a read access bit 22 must be set when the
second word is written to the Tx_FIFO. The least significant 8 bits of the second word contain the number of bytes
to receive. If the stop bit is never set, the XPS IIC will continue to own the IIC bus.
Pseudo Code for Dynamic IIC accesses:
It is recommended to verify that the Tx_FIFO is not full or will not overflow with the writing of new data. For read
accesses the user should reset the Rc_FIFO or check that SR(Rc_FIFO_Empty)=1.
Initialization
• Set Rc_FIFO depth to maximum by setting Rc_FIFO_PIRQ=0x0F
• Set 7 bit address mode
• Reset Tx_FIFO
• Enable XPS IIC, remove Tx_FIFO reset, disable general call
Read 4 bytes from an IIC device addressed as 0x34
• Check all FIFOs empty and bus not busy by reading status register
• Write 0x135 to Tx_FIFO (set start bit, device address to 0x34, read access)
• Write 0x204 to Tx_FIFO (set stop bit, 4 bytes to be received by the XPS IIC)
• Wait for Rc_FIFO not empty
- Read Rc_FIFO byte
- If 4^th byte read, then exit otherwise continue checking Rc_FIFO not empty
Write 4 bytes (0x89, 0xAB, 0xCD, 0xEF) to an IIC slave EEPROM device addressed as 0x34
Place the data at EEPROM address 0x33.
• Check all FIFOs empty and bus not busy by reading status register
• Write 0x134 to Tx_FIFO (set start bit, device address, write access)
• Write 0x33 to Tx_FIFO (EEPROM address for data)
• Write 0x89 to Tx_FIFO (byte 1)
• Write 0xAB to Tx_FIFO (byte 2)
• Write 0xCD to Tx_FIFO (byte 3)
• Write 0x2EF to Tx_FIFO (stop bit, byte 4)
DS606 June 22, 2011
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Product Specification