DS606 Datasheet, PDF (3/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
The dynamic logic is controlled by a start and stop bit that is located in the transmit FIFO. If neither of these bits are
set, then the dynamic logic is disabled. Both of these bits are included in the FIFO and are acted upon as the
Tx_FIFO is emptied.
Signal Filtering
The Philips Specification for I2C indicates that 0 to 50 ns of pulse rejection may be applied when operating in fast
mode (>100 kHz). The user may specify the max amount allowed by the specification or more through the filtering
parameters C_SCL_INERTIAL_DELAY and C_SDA_INERTIAL_DELAY. These parameters specify the amount of
delay in clock cycles.
Some designs may not require any filtering and others (even those operating below <100 kHz) may require the
maximum amount -- and possibly more. It depends on many factors beyond the control of the core itself. It may be
necessary for the user to experiment to determine the optimum amount. In the event that more the 50 ns of pulse
rejection is required it may be necessary for the user to more tightly constrain rise/fall times beyond what is
required by the Philips specification to accommodate the additional delay occurring because of the filter operation.
Design Parameters
To meet system resource or performance requirements the user may uniquely tailor the features of the XPS IIC
instance via its design parameters. Table 1 provides a comprehensive list of parameters and the corresponding
features configurable by the user.
Table 1: XPS IIC Design Parameters
Generic Feature / Description Parameter Name
Allowable Values
Default
Value
VHDL
Type
System Parameter
G1 Device Family
C_FAMILY
spartan3a, aspartan3a, spartan3,
aspartan3, spartan3e, aspartan3e,
spartan3adsp, aspartan3adsp,
spartan6, virtex4, qvirtex4, qrvirtex4,
virtex5, virtex5fx, virtex6, virtex6cx
virtex5
string
PLB Interface Parameters
G2 Device base address
C_BASEADDR
Valid Word Aligned Address⁽¹⁾
None⁽²⁾
std_logic_
vector
G3
Device maximum
address
C_HIGHADDR
C_HIGHADDR -C_BASEADDR
must be a power of 2 >= to
C_BASEADDR+1FFF⁽¹⁾
None⁽²⁾
std_logic_
vector
G4 PLB Master ID Width
C_SPLB_MID_WIDTH
log₂(C_SPLB_NUM_MASTERS)
with a minimum value of 1
1
integer
G5
Number of PLB Masters
C_SPLB_NUM_
MASTERS
1 to 16
1
integer
G6
Width of the PLB Least
Significant Address Bus
C_SPLB_AWIDTH
32
32
integer
G7
Width of the PLB Data
Bus
C_SPLB_DWIDTH
32, 64, 128
32
integer
XPS IIC Features
Maximum frequency of
G8
the master mode
generated SCL clock
C_IIC_FREQ
signal (Hz)
Less than or equal to 400KHz for
Fast Mode definition⁽³⁾
100E3
integer
DS606 June 22, 2011
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Product Specification