DS606 Datasheet, PDF (23/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Throttling is independent of Master or Slave operation and depends upon transmit or receive operation only.
However initiation of stops and repeated starts may only be accomplished at times when throttling is occurring and
only the XPS IIC acting as a Master may initiate such actions. When the XPS IIC is addressed as a Slave the
throttling mechanism gives the firmware time to, either (A) gather data for transmission from the Tx_FIFO, or (B) to
find a place to store data received into the Rx_FIFO.
Transmit throttling occurs when the transmit FIFO goes empty (except when a stop condition is pending.) When
one or more bytes are written into the Tx_FIFO, the transmit throttle condition is removed. The automatic throttling
provides the firmware with time to handle the interrupt processing necessary for data transfer without manually
having to manage the low level SCL signalling details. To prevent the throttle condition from re-appearing when the
TX_FIFO goes empty the firmware must setup the Master to issue a stop condition by reseting the CR(MSMS) bit
while the bus is throttled and prior to writing the very last byte to be transmitted to the Tx_FIFO.
To switch transmission to a new device while throttled a repeated start can be issued. The firmware does this by
setting the Control Register (CR) RSTA bit then writing the device address into the Tx_FIFO. The controller
recognizes this sequence, issues the repeated start, retrieves the address byte from the Tx_FIFO and outputs it onto
the bus. If no more data was placed into the Tx_FIFO the controller will immediately throttle again.
Receive throttling is done when the Receive FIFO Occupancy Register (Rc_FIFO_OCY) matches the value set in the
Receive FIFO Programmable Depth Interrupt Register (Rc_FIFO_PIRQ). The throttle condition is removed
(momentarily), when a byte from the Receive FIFO is read, thus allowing the transmitter to send the next byte. The
slow rate of IIC transmissions should permit the firmware to completely empty the receive fifo prior to the receipt
of the next byte but it is not necessary to do so.
When the XPS IIC is a master and a receive throttle condition exists, the XPS IIC generates a stop condition if the
Control Register (CR) MSMS bit is changed from a 1 to a 0. This allows single byte reads from a slave device. The
Control Register (CR) TXAK must be set equal to 1 to not-acknowledge the byte if desired.
When the XPS IIC is a master, is in a receive throttle condition and the transmit FIFO is empty, setting the repeated
start in the Control Register will cause a transmit throttle condition to occur. That would raise the Interrupt(2) --
Transmit FIFO Empty flag.
Standard Controller Logic Flow
The following is a brief discussion on setting the XPS IIC registers to initiate and complete bus transactions.
IIC Master Transmitter, with a repeated start
1. Write the IIC device address to the Tx_FIFO.
2. Write data to Tx_FIFO.
3. Write to Control Register (CR) to set MSMS = 1 and TX = 1.
4. Continue writing data to Tx_FIFO.
5. Wait for Transmit FIFO empty interrupt. This implies the IIC has throttled the bus.
6. Write to CR to set RSTA = 1.
7. Write IIC device address to Tx_FIFO.
8. Write all data except last byte to Tx_FIFO.
9. Wait for Transmit FIFO empty interrupt. This implies the IIC has throttled the bus.
10. Write to CR to set MSMS = 0. The IIC generates a stop condition at the end of the last byte.
11. Write last byte of data to Tx_FIFO.
DS606 June 22, 2011
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Product Specification