DS606 Datasheet, PDF (18/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Table 12: XPS IIC Receive FIFO (C_BASEADDR + 0x10C)
Bit(s)
Name
Access
Reset Value
0 - 23
24 - 31
Reserved
D0 - D7
N/A
Read
N/A
Indeterminate ⁽¹⁾
Reserved
IIC Receive Data
Description
Notes:
1. The value that was available before the reset occurred appears on the FIFO outputs
Slave Address Register (ADR)
The user programs the ADR register (and possibly the TEN_ADR register) to set the address at which the slave will
acknowledge an address transfer operation from the bus master. The slave address field of the ADR register
contains all 7-bits of the 7-bit address or the least significant 7-bits of the 10-bit address the XPS IIC Bus Interface
recognizes when operating as a slave. Figure 10 illustrates the field layout of the register and Table 13 provides the
detailed field descriptions.
Figure Top x-ref 10
Slave
Address
Reserved
0
23 24
30 31
Reserved
Figure 10: Address Register (ADR)
Table 13: Address Register (C_BASEADDR + 0x110)
Bit(s)
Name
Access
Reset
Value
Description
0 - 23
Reserved
N/A
N/A
Reserved
24-30 Slave Address Read/Write
0x00 Address used by the IIC Bus Interface when in Slave mode
31
Reserved
N/A
N/A
Reserved
Slave Ten Bit Address Register (TEN_ADR)
The user programs the ADR register (and possibly the TEN_ADR register) to set the address at which the slave will
acknowledge and address transfer operation from the bus master. The slave address field of the TEN_ADR register
contains the most significant 3-bits of the 10-bit address the XPS IIC Bus Interface recognizes when operating as a
10-bit addressable slave. This register exists only if the user configures the XPS IIC for 10-bit addressing by setting
generic parameter C_TEN_BIT_ADR to 1. The TEN_ADR register is shown in Figure 11 and described in Table 14.
Figure Top x-ref 11
Slave
Address
0
28 29
31
Reserved
Figure 11: Ten Bit Address Register (TEN_ADR)
DS606 June 22, 2011
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Product Specification