DS606 Datasheet, PDF (31/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Figure Top x-ref 20
MPMC5
XPS CDMA
XPS CDMA
Device Under
Test (DUT)
MicroBlaze^™
Processor
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
MDM
Figure 20: Spartan-6 System
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately 70% and the
I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target F_MAX (frequency maximum) values are shown in Table 24.
Table 24: XPS IIC Controller Estimated System Performance
Target FPGA
S3ADSP3400-4
Target F_MAX (MHz)
90
S6LX45T-2
92
V4FX60-10
100
V5FXT70-1
120
V6LX130T-1
136
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
XPS IIC Limitation
This core provides 0 ns SDA hold time in master mode operation as mentioned in Philips IIC bus specification. If
any IIC slave requires additional hold time, this can be achieved by adding delay on
SCL(C_SCL_INERTIAL_DELAY). Please refer the description of this parameter.
The dynamic controller logic in XPS IIC controller supports master mode operation and 7-bit addressing only.
Specification Exceptions
Exceptions to the Philips IIC-bus specification version 2.1 January 2000
High-speed mode (Hs-mode) is not currently supported by the XPS IIC IP.
3-state buffers are used to perform the wired-AND function inherent in this bus structure.
The Xilinx FPGA device ratings must not be exceeded when inter-connecting the XPS IIC to other devices.
The t_BUF parameter ("Bus free time between a STOP and START condition", Table 5, Page 32 Philips I²C-bus
Specification) is not met by the controller. The user must ensure the proper delay specification is met if the core is
utilized with a bus device that needs the extra delay.
DS606 June 22, 2011
www.xilinx.com
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Product Specification