DS606 Datasheet, PDF (27/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Read 4 bytes from an IIC slave EEPROM device addressed as 0x34
The data is at EEPROM address 0x33. First, a write access is necessary to set the EEPROM address, then a repeated
start follows with the read accesses:
• Check all FIFOs empty and bus not busy by reading the status register
• Write 0x134 to Tx_FIFO (set start bit, device address to 0x34, write access)
• Write 0x33 to Tx_FIFO (EEPROM address for data)
• Write 0x135 to Tx_FIFO (set start bit for repeated start, device address 0x34, read access)
• Write 0x204 to Tx_FIFO (set stop bit, 4 bytes to be received by the XPS IIC)
• Wait for Rc_FIFO not empty
- Read Rc_FIFO byte
- If 4^th byte is read, exit; otherwise, continue checking Rc_FIFO not empty
Timing Diagrams
N/A
Design Constraints
N/A
Design Implementation
Target Technology
The target technology is an FPGA listed in EDK Supported Device Families.
Device Utilization and Performance Benchmarks
Since the XPS IIC core will be used with other design modules in the FPGA, the utilization and timing numbers
reported in this section are estimates only. When the XPS IIC core is combined with other designs in the system, the
utilization of FPGA resources and timing of the XPS IIC design will vary from the results reported here.
The XPS IIC resource utilization for various parameter combinations measured with Virtex-5 as the target device
are detailed in Table 19.
Table 19: Performance and Resource Utilization Benchmarks on Virtex-5 (xc5vfx70-ff1136-1)
Parameter Values
Device Resources
Performance
C_IIC_FREQ
C_TEN_
BIT_ADR
C_GPO_
WIDTH
C_SCL/SDA
_INERTIAL_
DELAY
Slices
Slice
Flip-Flops
LUTs
F_MAX (MHz)
100,000
0
1
0
261
306
410
174
400,000
0
1
0
251
304
397
158
400,000
1
1
5
275
313
415
155
400,000
0
1
5
251
304
397
158
400,000
0
8
5
248
311
401
160
DS606 June 22, 2011
www.xilinx.com
27
Product Specification