DS606 Datasheet, PDF (7/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Table 2: XPS IIC I/O Signal Description (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
P23 PLB_rdBurst
PLB
I
- PLB burst read transfer
P24 PLB_wrPendReq
PLB
I
- PLB pending bus write request
P25 PLB_rdPendReq
PLB
I
- PLB pending bus read request
P26 PLB_rdPendPri[0 : 1]
PLB
I
- PLB pending read request priority
P27 PLB_wrPendPri[0 : 1]
PLB
I
- PLB pending write request priority
P28 PLB_reqPri[0 : 1]
PLB
I
- PLB current request priority
PLB Slave Interface Signals
P29 Sl_addrAck
PLB
O
0 Slave address acknowledge
P30 Sl_SSize[0 : 1]
PLB
O
0 Slave data bus size
P31 Sl_wait
PLB
O
0 Slave wait indicator
P32 Sl_rearbitrate
PLB
O
0 Slave rearbitrate bus indicator
P33 Sl_wrDack
P34 Sl_wrComp
PLB
O
0 Slave write data acknowledge
PLB
O
0 Slave write transfer complete indicator
P35
Sl_rdBus[0 :C_SPLB_
DWIDTH-1]
PLB
O
0 Slave read data bus
P36 Sl_rdDack
PLB
O
0 Slave read data acknowledge
P37 Sl_rdComp
PLB
O
0 Slave read transfer complete indicator
P38
Sl_MBusy[0 :C_SPLB_NUM_
MASTERS - 1]
PLB
O
0 Slave busy indicator
P39
Sl_MWrErr[0 :C_SPLB_NUM_
MASTERS - 1]
PLB
O
0 Slave write error indicator
P40
Sl_MRdErr[0 :C_SPLB_NUM_
MASTERS - 1]
PLB
O
0 Slave read error indicator
Unused PLB Slave Interface Signals
P41 Sl_wrBTerm
PLB
O
0 Slave terminate write burst transfer
P42 Sl_rdWdAddr[0 : 3]
PLB
O
0 Slave read word address
P43 Sl_rdBTerm
PLB
O
0 Slave terminate read burst transfer
Sl_MIRQ[0 :
P44 C_SPLB_NUM_MASTERS -
PLB
O
0 Master interrupt request
1]
IIC Signals
P45 Sda_I
System
I
- IIC Serial Data Input from 3-state buffer.
P46 Sda_O
P47 Sda_T
System
O
System
O
0 IIC Serial Data Output to 3-state buffer
0 IIC Serial Data Output Enable to 3-state buffer⁽¹⁾
P48 Scl_I
System
I
- IIC Serial Clock Input from 3-state buffer
P49 Scl_O
P50 Scl_T
System
O
System
O
0 IIC Serial Clock Output to 3-state buffer
0 IIC Serial Clock Output Enable to 3-state buffer⁽¹⁾
DS606 June 22, 2011
www.xilinx.com
7
Product Specification