DS606 Datasheet, PDF (14/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
See Figure 5 for an illustration of the SOFTR bit fields and Table 8 for a description of the SOFTR bit fields.
Figure Top x-ref 5
RKEY
0
27 28
31
Reserved
Figure 5: Soft Reset Register (SOFTR)
Table 8: Soft Reset Register (C_BASEADDR + 0x040)
Bit(s)
Name Core Access Reset Value
Description
0-27 Reserved
N/A
N/A
Reserved
28-31
RKEY
Write
Reset Key. The firmware must write a value of 0xA to this field to
N/A
cause a soft reset of the Interrupt registers of XPS IIC controller.
Writing any other value results in a PLB transaction
acknowledgement with error and no reset occurs.
Control Register (CR)
Writing to the CR register configures the XPS IIC operation mode and simultaneously allows for IIC transactions to
be kicked off.
Prior to setting Master Slave Mode Select (MSMS) to a 1, Tx_FIFO should contain the address of the XPS IIC device.
All the CR bits can be set at the same time as setting MSMS to a 1 to initiates a bus transaction.
When initiating a repeated start condition, the transmit FIFO must be empty. First, set the repeated start bit to a 1
and then write the address of the XPS IIC device to the transmit FIFO. The rest of the FIFO can be filled with data,
if required.
The EN field provides a way for the device driver to initialize interrupts prior to enabling the device to
send/receive data.
The XPS IIC Control Register is shown in Figure 6 and described in Table 9.
Figure Top x-ref 6
GC_EN TXAK MSMS EN
0
24 25 26 27 28 29 30 31
Reserved
RSTA TX TxFIFO
Figure 6: Control (CR) Register
DS606 June 22, 2011
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Product Specification