DS606 Datasheet, PDF (20/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Table 16: Receive FIFO Occupancy Register (C_BASEADDR + 0x118)
Bit(s)
Name
Access
Reset
Value
Description
0 - 27
Reserved
N/A
N/A
Reserved
28 - 31 Occupancy Value
Read
0x0
Bit 28 is the MSB. A value of 1001 implies that 10 locations in
the FIFO are full.
Receive FIFO Programmable Depth Interrupt Register (Rc_FIFO_PIRQ)
This field contains the value which causes the receive FIFO Interrupt to be set. When this value is equal to the
Rc_FIFO_OCY value, the receive FIFO interrupt is set and remains set until the equality is no longer true. A read
from the receive FIFO will cause the IIC Receive FIFO Interrupt to be cleared. When the Rc_FIFO_PIRQ is equal to
the Rc_FIFO_OCY throttling will also occur to prevent the transmitter from transmitting. The read/write
Rc_FIFO_PIRQ register is shown in Figure 14 and described in Table 17.
Figure Top x-ref 14
Compare
Value
0
27 28 31
Reserved
Figure 14: Receive FIFO Programmable Depth Interrupt Register (Rc_FIFO_PIRQ)
Table 17: Receive FIFO Programmable Depth Interrupt Register (C_BASEADDR + 0x120)
Bit(s)
Name
Access
Reset
Value
Description
0 - 27
Reserved
N/A
N/A
Reserved
28 - 31 Compare Value Read/Write
Bit 28 is the MSB. A value of 1001 implies that when ten
0x0
locations in the receive FIFO are filled, the receive FIFO
interrupt will be set.
General Purpose Output Register (GPO)
The current value of the General Purpose Output field of the GPO register is reflected continuously on the GPO
signal of the pcore. Thus the GPO signal of the pcore could be used to set an IIC memory device write protect for
example.
If C_GPO_WIDTH is equal to one, the only bit populated in the register is GPO(31), the LSB. If C_GPO_WIDTH is
equal to 8, then bits 24 through 31 in the GPO are populated. Reading unpopulated bits results in indeterminate
data.
DS606 June 22, 2011
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Product Specification