DS606 Datasheet, PDF (19/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Table 14: Ten Bit Address Register (C_BASEADDR + 0x11C)
Bit(s)
Name
Access
Reset
Value
Description
0 - 28 Reserved
N/A
N/A Reserved
29 - 31
MSB of Slave
Address
Read/Write
0x0
3 MSBs of the 10-bit Address used by the XPS IIC Bus Interface when
in Slave mode.
Transmit FIFO Occupancy Register (Tx_FIFO_OCY)
This field contains the occupancy value for the Transmit FIFO. Reading this register cannot be used to determine if
the FIFO is empty. The Transmit FIFO Empty Interrupt conveys that information. The value read is the occupancy
value minus one, therefore reading all zeros indicates that the first location is filled and reading all ones implies that
all sixteen locations are filled. The Tx_FIFO_OCY register is shown in Figure 12 and described in Table 15.
Figure Top x-ref 12
Transmit
Occupancy
0
27 28
31
Reserved
Figure 12: Transmit FIFO Occupancy Register (Tx_FIFO_OCY)
Table 15: Transmit FIFO Occupancy Register (C_BASEADDR + 0x114)
Bit(s)
Name
Access Reset Value
Description
0 - 27
Reserved
N/A
N/A
Reserved
28 -31 Occupancy Value
Read
0x0
Bit 28 is the MSB. A value of 1001 indicates that 10 locations
in the FIFO are full.
Receive FIFO Occupancy Register (Rc_FIFO_OCY)
This field contains the occupancy value for the Receive FIFO. This register is read only. Reading this register cannot
be used to determine if the FIFO is empty. Rc_FIFO_Empty, bit(1) in the status register is used to convey that
information. The value read is the occupancy value minus one, therefore reading all zeros implies that the first
location is filled and reading all ones implies that all sixteen locations are filled. The Rc_FIFO_OCY register is
shown in Figure 13 and described in Table 16.
Figure Top x-ref 13
Receive
Occupancy
0
27 28
31
Reserved
Figure 13: Receive FIFO Occupancy Register (Rc_FIFO_OCY)
DS606 June 22, 2011
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Product Specification