DS606 Datasheet, PDF (8/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Table 2: XPS IIC I/O Signal Description (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
P51 Gpo(32 - C_GPO_WIDTH: 31) System
O
0 General Purpose Outputs
Notes:
1. The Sda_T and Scl_T signals are the 3-state enable signals that control the data direction for the Sda and Scl signal.
Parameter - Port Dependencies
The width of some of the XPS IIC signals depends on parameters selected in the design. The dependencies between
the XPS IIC design parameters and I/O signals are shown in Table 3.
Table 3: XPS IIC Parameter Port Dependencies
Generic
or Port
Name
Affects Depends
Relationship Description
Design Parameters
G3 C_HIGHADDR
-
G2
Address range pair dependency
G4 C_SPLB_MID_WIDTH
Affects the width of current master identifier
P6
G5
signals and depends on
log₂(C_SPLB_NUM_MASTERS) with a
minimum value of 1
G5 C_SPLB_NUM_MASTERS
P38, P39,
P40, P44
-
Affects the width of busy and error signals
G7 C_SPLB_DWIDTH
P8, P11,
P35
-
Affects number of bits in slave data bus
G10 C_GPO_WIDTH
P51
-
Specifies signal vector width
I/O Signals
P6 PLB_masterID
-
G4
Width varies with the size of the PLB master
identifier bus
P8 PLB_BE
-
G7
Width varies with the value of
C_SPLB_DWIDTH/8
P11 PLB_wrDBus
-
G7
Width varies with the value of C_SPLB_DWIDTH
P35 Sl_rdDBus
-
G7
Width varies with the value of C_SPLB_DWIDTH
P38 Sl_MBusy
-
G5
Width varies with the value of
C_SPLB_NUM_MASTERS
P39 Sl_MWrErr
-
G5
Width varies with the value of
C_SPLB_NUM_MASTERS
P40 Sl_MRdErr
-
G5
Width varies with the value of
C_SPLB_NUM_MASTERS
P44 Sl_MIRQ
-
G5
Width varies with the value of
C_SPLB_NUM_MASTERS
P51 GPO
-
G10 Width varies with the value of C_GPO_WIDTH
DS606 June 22, 2011
www.xilinx.com
8
Product Specification