DS606 Datasheet, PDF (13/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Table 6: Interrupt Status Register (C_BASEADDR + 0x020)
Bit(s)
Name
Core Access
Reset
Value
Description
0 - 23
Reserved
N/A
N/A
Reserved
24
int(7)
Read/Toggle on Write
1
Interrupt(7) -- Transmit FIFO Half Empty
25
int(6)
Read/Toggle on Write
1
Interrupt(6) -- Not Addressed As Slave
26
int(5)
Read/Toggle on Write
0
Interrupt(5) -- Addressed As Slave
27
int(4)
Read/Toggle on Write
1
Interrupt(4) -- IIC Bus is Not Busy
28
int(3)
Read/Toggle on Write
0
Interrupt(3) -- Receive FIFO Full
29
int(2)
Read/Toggle on Write
0
Interrupt(2) -- Transmit FIFO Empty
30
int(1)
Read/Toggle on Write
0
Interrupt(1) -- Transmit Error/Slave Transmit Complete
31
int(0)
Read/Toggle on Write
0
Interrupt(0) -- Arbitration Lost
Interrupt Enable Register (IER)
The firmware uses the fields of this register to enable or disable interrupts needed to manage either the Standard
Controller Logic Flow or the Dynamic Controller Logic Flow.
Table 7: Interrupt Enable Register (C_BASEADDR + 0x028)
Bit(s)
Name
Core Access Reset Value
Description
0 - 23
Reserved
N/A
N/A
Reserved
24
int(7)
Read/Write
0
Interrupt(7) -- Transmit FIFO Half Empty
25
int(6)
Read/Write
0
Interrupt(6) -- Not Addressed As Slave
26
int(5)
Read/Write
0
Interrupt(5) -- Addressed As Slave
27
int(4)
Read/Write
0
Interrupt(4) -- IIC Bus is Not Busy
28
int(3)
Read/Write
0
Interrupt(3) -- Receive FIFO Full
29
int(2)
Read/Write
0
Interrupt(2) -- Transmit FIFO Empty
30
int(1)
Read/Write
0
Interrupt(1) -- Transmit Error/Slave Transmit Complete
31
int(0)
Read/Write
0
Interrupt(0) -- Arbitration Lost
Notes:
1. In any given bit position, 1=Interrupt enabled, 0=Interrupt masked
Soft Reset Register (SOFTR)
The firmware can write to the SOFTR to initialize all the XPS IIC registers to its default state. To accomplish this the
firmware must write the reset key value of 0xA to the least significant nibble of the 32-bit word. After recognizing
a write of 0xA the proc_common soft_reset module issues a pulse 4 clocks long to reset the XPS IIC. At the end of
the pulse the SOFTR acknowledges the PLB transaction. That prevents anything further from happening while the
reset occurs.
Writing any value to bits 28:31 other then 0xA results in a PLB transaction acknowledge with an error status.The
register is not readable.
Applying soft reset to XPS IIC core also clears the bus busy status (bit-29 of SR) which may not give the correct
status of the IIC bus, if IIC bus is locked by other IIC slave. Hence user should reset external slave after the
application of the soft reset to the XPS IIC core prior using the IIC bus again.
DS606 June 22, 2011
www.xilinx.com
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Product Specification