DS606 Datasheet, PDF (29/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
The XPS IIC resource utilization for various parameter combinations measured with Spartan-6 as the target device
are detailed in Table 23.
Table 23: Performance and Resource Utilization Benchmarks on Spartan-6 (xc6slx45t-fgg484-2)
Parameter Values
Device Resources
Performance
C_IIC_FREQ
C_TEN_
BIT_ADR
C_GPO_
WIDTH
C_SCL/SDA_
INERTIAL_
DELAY
Slices
Slice
Flip-Flops
LUTs
F_MAX (MHz)
100,000
0
1
0
214
315
453
100
400,000
0
1
0
167
311
427
100
400,000
1
1
5
183
320
440
100
400,000
0
1
5
167
311
421
100
400,000
0
8
5
197
318
446
100
Note: The generic parameters used in the utilization tables are given below.
1. C_CLK_FREQ=100000000
2. C_BASEADDR=X"00000000"
3. C_HIGHADDR=X"000001FF"
4. C_SPLB_MID_WIDTH=1
5. C_SPLB_NUM_MASTERS=1
6. C_SPLB_AWIDTH=32
7. C_SPLB_DWIDTH=32
System Performance
To measure the system performance (F_MAX) of this core, this core was added to a Virtex-4 system, a Virtex-5 system,
a Spartan-3ADSP, a Virtex-6 system and a Spartan-6 system as the Device Under Test (DUT) as shown in Figure 16,
Figure 17, Figure 18, Figure 19, and Figure 20.
Because the XPS IIC core will be used with other design modules in the FPGA, the utilization and timing numbers
reported in this section are estimates only. When the XPS IIC core is combined with other designs in the system, the
utilization of FPGA resources and timing of the XPS IIC design will vary from the results reported here.
Figure Top x-ref 16
PLBV46
PLBV46
MPMC5
XPS CDMA
XPS CDMA
Device Under
Test (DUT)
IPLB1 DPLB1
PowerPC ^®405 ^DPLB0
Processor
IPLB0
PLBV46
XPS BRAM
XPS INTC
XPS GPIO
XPS UART
Lite
Figure 16: Virtex-4 FX System
DS606 June 22, 2011
www.xilinx.com
29
Product Specification