DS606 Datasheet, PDF (17/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Transmit FIFO (Tx_FIFO)
This is the keyhole address for the FIFO that contains data to be transmitted on the IIC bus. In transmit mode, data
written into this FIFO is output on the IIC bus. Reading of this location will result in reading the current byte being
output from the FIFO. Attempting to write to a full FIFO is not recommended and results in that data byte being
lost. Firmware must clear the FIFO prior to use in anticipation of it not being empty possibly do to abnormal IIC
protocol abnormal terminations or other normal controller actions such as dynamic mode reads. The Transmit FIFO
(Tx_FIFO) is shown in Figure 8 and described in Table 11.
Figure Top x-ref 8
Start
Tx Data
0
21 22 23 24
31
Reserved
Stop
Figure 8: Transmit FIFO (Tx_FIFO)
Table 11: XPS IIC Transmit FIFO (C_BASEADDR + 0x108)
Bit(s) Name
Access
Reset Value
Description
0 - 21 Reserved
N/A
N/A
Reserved
22
Stop Read/Write
Stop. The dynamic stop bit may be used to send an IIC
0
stop sequence on the IIC bus after the last byte has been
transmitted or received. ⁽²⁾
23
Start Read/Write
Start. The dynamic start bit may be used to send a start
0 ⁽¹⁾
or repeated start sequence on the IIC bus. A start
sequence is generated if the MSMS = 0, a repeated start
sequence is generated if the MSMS = 1. ⁽²⁾
24 - 31
D0 - D7
XPS IIC Transmit Data. If the dynamic Stop bit is used
Read/Write Indeterminate ⁽¹⁾ and the XPS IIC is a master receiver, the value is the
number of bytes to receive. ⁽³⁾
Notes:
1. The value that was available before the reset occurred will still appear on the FIFO outputs
2. A full description for the use of the dynamic stop and start bits is contained in the Dynamic Controller Logic Flow
section. These bits are not readable
3. Only bits 24-31 can be read back.
Receive FIFO (Rc_FIFO)
This FIFO contains the data received from the IIC bus. The received IIC data is placed in this FIFO after each
complete transfer. The Receive FIFO Occupancy Register (Rc_FIFO_OCY) must be equal to the Receive FIFO
Programmable Depth Interrupt Register (Rc_FIFO_PIRQ) before throttling occurs. The receive FIFO is read only. Reading
this FIFO when it is empty results in indeterminate data being read. The Receive FIFO is shown in Figure 9 and
described in Table 12.
Figure Top x-ref 9
Rc Data
0
23 24
31
Reserved
Figure 9: Receive FIFO (Rc_FIFO)
DS606 June 22, 2011
www.xilinx.com
17
Product Specification