DS606 Datasheet, PDF (11/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Once successful Slave addressing is achieved, the data transfer proceeds byte-by-byte in the direction as specified
by the read/write bit.
The Master can terminate the communication by generating a STOP signal to free the bus when the receiver signals
a not-acknowledge (signaled by releasing SDA during the acknowledgement clock period.) However, the Master
may generate a START signal without generating a STOP signal first. This is called a repeated START. A repeated
start allows the master to change the direction of data transfer or address a different slave without giving up the
bus.
XPS IIC Register Descriptions
Table 4 specifies the name, offset and accessibility of each firmware addressable register from the three classes of
registers within the XPS IIC pcore. User access to each register is from an offset to the base address set the
C_BASEADDR parameter. For example, C_BASEADDR + 0x100 represents the address of the Table 4.
Table 4 shows all of the XPS IIC registers and their addresses.
Table 4: XPS IIC Registers
Base Address + Offset
(hex)
Register Name
Access Type
C_BASEADDR + 0x01C
C_BASEADDR + 0x020
C_BASEADDR + 0x028
Interrupt Registers
Global Interrupt Enable (GIE) ⁽¹⁾
Interrupt Status Register (ISR) ⁽¹⁾
Interrupt Enable Register (IER)⁽¹⁾
Read/Write
Read/Toggle ⁽³⁾ on
Write
Read/Write
C_BASEADDR + 0x040
Soft Reset
Soft Reset Register (SOFTR) ⁽²⁾
Write Only
IIC Configuration, Control, Data
C_BASEADDR + 0x100 Control Register (CR)
Read/Write
C_BASEADDR + 0x104 Status Register (SR)
Read
C_BASEADDR + 0x108 Transmit FIFO (Tx_FIFO)
Read/Write
C_BASEADDR + 0x10C Receive FIFO (Rc_FIFO)
Read
C_BASEADDR + 0x110 Slave Address Register (ADR)
Read/Write
C_BASEADDR + 0x114
Transmit FIFO Occupancy Register
(Tx_FIFO_OCY)
Read
C_BASEADDR + 0x118
Receive FIFO Occupancy Register
(Rc_FIFO_OCY)
Read
C_BASEADDR + 0x11C Slave Ten Bit Address Register (TEN_ADR) Read/Write
C_BASEADDR + 0x120
Receive FIFO Programmable Depth Interrupt
Register (Rc_FIFO_PIRQ)
Read/Write
C_BASEADDR + 0x124 General Purpose Output Register (GPO)
Read/Write
Default value (hex)
0x00
0xD0
0x00
N/A
0x00
0xC0
0x00
N/A
0x00
0x00
0x00
0x00
0x0
0x0
Notes:
1. See page 11, product data sheet DS516 Interrupt Control V2.01a, July 2, 2008
2. The soft reset functionality is implemented by the proc_common soft_reset module now
3. Toggle each bit position to which a ’1’ is written
DS606 June 22, 2011
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Product Specification