DS606 Datasheet, PDF (25/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
a. Set the Receive FIFO interrupt register to 0x0 and wait for either a Not Addressed as Slave NAS interrupt
(no data was sent) or Rc_FIFO_PIRQ interrupt. In this mode, an interrupt occurs for every byte of data
received plus a NAS for the end of the transmission.
b. Set the Receive FIFO interrupt register to 0xF and wait for either a Not Addressed as Slave NAS (some
amount of data less than 16 bytes was set) or Rc_FIFO_PIRQ interrupt. In this mode if the Rc_FIFO_PIRQ
interrupt occurs then 16 bytes of data exists in the FIFO to handle. Xilinx recommends that the software
read the Receive FIFO occupancy register though not required. NAS may occur without Rc_FIFO_PIRQ
interrupt. That means the Receive FIFO occupancy register should be read to indicate how many bytes of
data must be handled. In this mode there is one Rc_FIFO_PIRQ interrupt for every 16 bytes of data plus a
NAS for the end of the transmission. If less than 16 bytes of data is sent, NAS is the only interrupt.
8. In either choice above, clear the active interrupts after the data has been handled and then wait for the next
interrupt.
9. Once the NAS interrupt has been received, handle the data and clear AAS.
10. Wait for the AAS interrupt.
IIC Slave Transmitter
1. If the IIC is a slave transmitter, the following interrupt processing is available for use:
2. Ensure the Transmit Error/Slave Transmit Complete interrupt is cleared.
3. Once the IIC has been addressed as a slave transmitter the IIC will transmit the first byte of data in the Transmit
FIFO. If no data exists in the transmit FIFO, the IIC will throttle the bus until data is written into the transmit
FIFO.
4. If the protocol allows knowledge as to how much data the slave must transmit, fill up the FIFO and use the
Transmit FIFO Empty or Transmit FIFO Half Empty interrupts to keep the transmit FIFO full. Wait for the
Transmit Error/Slave Transmit Complete interrupt.
5. It is possible to write one byte of data at a time to the FIFO, then wait for a Transmit FIFO empty interrupt which
means the master wants more data, or wait for the Transmit Error/Slave Transmit Complete interrupt which
indicates that the master has received the required data.
6. When Transmit Error/Slave Transmit Complete has occurred, the NAS also occurs because the master has to
either send a stop or send a repeated start.
7. When the NAS interrupt has been received, handle the data and clear AAS.
8. Wait for the AAS interrupt.
Dynamic Controller Logic Flow
For initialization both the Receive FIFO (Rc_FIFO) and Transmit FIFO (Tx_FIFO) should be empty, and the XPS IIC
should be enabled by setting Control Register (CR) EN = 1.
Start/Repeated Start Sequence:
When sending bytes of data over the IIC bus, the Tx_FIFO is filled first with the 7 bit device address of the IIC
peripheral and the read/write bit, and any required data. In order to wake up the dynamic logic, the device address
is written to the Transmit FIFO (Tx_FIFO) as a 16 bit word (10 bits are used by the XPS IIC) with the start bit set (bit
23). Then if a read is to be performed, write the receive byte count to the Tx_FIFO else put the data to be written to
it. When the dynamic logic detects that data is available in the Tx_FIFO and that the start bit is set, the XPS IIC will
do the following:
1. Check the control register to see if MSMS is already set
a. If MSMS is not set, then set the MSMS bit to create a start sequence
b. If MSMS is already set, then set the RSTA in the control register to create a repeated start sequence
DS606 June 22, 2011
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Product Specification