DS606 Datasheet, PDF (5/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
C_SCL_INERTIAL_DELAY, C_SDA_INERTIAL_DELAY
These parameters specify the number of SPLB_CLK cycles used to define the width of the pulse rejection. For
example, a 100 Mhz clock coupled with an C_SCL_INERTIAL_DELAY value of 5 gives 50 ns of pulse rejection. And,
incidentally, delays the signal internally by 50 ns.
Filtering SCL without filtering SDA can have potentially undesirable effects by causing SDA to change when SCL
is high resulting in false starts occurring.
Likewise, increasing the pulse rejection width for SDA beyond that for SCL may eliminate erroneous starts/stops
by increasing the SDA hold time. Although technically the Philips specification permits 0 ns of hold time, in practice
the sloppy signalling in IIC systems (caused by very large rise/fall times, due to high bus capacitance and high
pull-up resistance and/or the use of level translation mosfets) can result in failures due to the high speed sampling
of these analog signals.
In particular Virtex^®-5 I/O are so fast that the slow signal rise time plus noise exceeding the input hysteresis can
result in phantom pulses internal to the circuit. The filters remove these quite effectively.
XPS IIC core provides 0 ns SDA hold time in master mode operation. If any IIC slave requires additional hold time
on the SDA from the core, this can be achieved by adding delay on SCL (C_SCL_INERTIAL_DELAY). For example,
for 100 Mhz PLB clock, to have 300 ns hold time, C_SCL_INERTIAL_DELAY parameter should be configured for a
integer value of 30. The parameter C_SDA_INERTIAL_DELAY can be set to 0 to 5 as per the required pulse
rejection.
C_BASEADDR, C_HIGHADDR
These two parameters determine the address range in PLB address space where the XPS IC registers reside.
The address range defined by C_BASEADDR and C_HIGHADDR for the XPS IIC must be a power of 2 and greater
then or equal to 512 bytes (0x200). For example, if C_BASEADDR = 0xE0000000 then C_HIGHADDR must be
0xE0000200, 0xE0000400, ..., etc.
C_SPLB_MID_WIDTH
This parameter is defined as an integer and has a minimum value of 1. It is equal to log₂ of the number of PLB
Masters connected to the PLB bus or 1, whichever is greater. It is used to size the PLB_masterID bus input from the
PLB Bus to the Slave Attachment. For example, if eight PLB Masters are connected to the PLB Bus, then this
parameter must be set to log₂(8) which is equal to 3. The PLB_masterID signal would then be sized to 3 bits wide.
If only one master exists, then the parameter needs to be set to 1.
C_SPLB_NUM_MASTERS
This parameter is defined as an integer and is equal to the number of Masters connected to the PLB bus. This
parameter is used to size the Sl_MBusy and Sl_MErr slave reply buses to the PLB. For example, if eight PLB Masters
are connected to the PLB Bus, then this parameter must be set to 8. The Sl_MBusy bus and Sl_MErr bus will be sized
to 8 bits wide each.
C_SPLB_AWIDTH
This integer parameter is used by the PLB Slave to size the PLB address related components within the Slave
Attachment. This value should be set 32.
C_SPLB_DWIDTH
This integer parameter is used by the PLB Slave to size PLB data bus related components within the Slave
Attachment. This value should be set to match the actual width of the PLB bus, 32, 64, or 128-Bits.
DS606 June 22, 2011
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Product Specification