DS606 Datasheet, PDF (15/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Table 9: XPS IIC Control Register (C_BASEADDR + 0x100)
Bit(s)
Name
Core Access
Reset
Value
Description
0- 24 Reserved
N/A
N/A Reserved
25
GC_EN Read/Write
General Call Enable. Setting this bit High allows the XPS IIC to respond
to a general call address.
0
"0" - General Call Disabled.
"1" - General Call Enabled.
26
RSTA
Read/Write
Repeated Start. Writing a “1” to this bit generates a repeated START
condition on the bus if the XPS IIC Bus Interface is the current bus Master.
0
Attempting a repeated START at the wrong time, if the bus is owned by
another Master, results in a loss of arbitration. This bit is reset when the
repeated start occurs. This bit must be set prior to writing the new
address to the Tx_FIFO or DTR.
27
TXAK
Read/Write
Transmit Acknowledge Enable. This bit specifies the value driven onto
the SDA line during acknowledge cycles for both Master and Slave
receivers.
“1” - ACK bit = “1” - not-acknowledge.
0
“0” - ACK bit = “0” - acknowledge.
Because Master receivers indicate the end of data reception by not
acknowledging the last byte of the transfer, this bit is used to end a Master
receiver transfer. As a slave, this bit must be set prior to receiving the byte
to signal a not-acknowledge.
Transmit/Receive Mode Select. This bit selects the direction of
Master/Slave transfers.
“1” selects an XPS IIC transmit.
28
TX
Read/Write
0
“0” selects an XPS IIC receive.
This bit does not control the Read/Write bit that is sent on the bus with the
address. The Read/Write bit that is sent with an address must be the LSB
of the address written into the Tx_FIFO.
29
MSMS Read/Write
Master/Slave Mode Select. When this bit is changed from 0 to 1, the
XPS IIC Bus Interface generates a START condition in Master mode.
0
When this bit is cleared, a STOP condition is generated and the XPS IIC
Bus Interface switches to Slave mode. When this bit is cleared by the
hardware, because arbitration for the bus has been lost, a STOP
condition is not generated. (See also: Arb Lost Interrupt)
30
Tx_FIFO
Reset
Read/Write
Transmit FIFO Reset. This bit must be set to flush the FIFO if either (a)
arbitration is lost or (b) if a transmit error occurs.
0
“1” resets the Transmit FIFO.
“0” Transmit FIFO normal operation.
XPS IIC Enable. This bit must be set before any other CR bits have any
effect.
31
EN
Read/Write
0
“1” enables the XPS IIC controller.
“0” resets and disables the XPS IIC controller but not the registers or
FIFOs.
DS606 June 22, 2011
www.xilinx.com
15
Product Specification