DS606 Datasheet, PDF (22/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
The firmware must clear this interrupt by writing a 1 to the Interrupt Status Register (ISR), INT(1) bit to toggle it.
Note that this interrupt will occur before the INT(4) if INT(4) is also enabled. (The stop occurs later.)
Interrupt(2) -- Transmit FIFO Empty
The controller raises (sets) the interrupt flag and keeps it raised while a transmit throttle condition exists. Once the
flag has been raised and the transmit throttle condition is removed then (and only then can) the firmware lower
(clear) the flag by writing a ’1’ to the Interrupt Status Register (ISR), INT(2) bit in order to toggle the flag state. See
Throttle Description for information on actions that must be taken to clear a transmit throttle condition. The usual
cause for a transmit throttle condition is the transmit FIFO going empty.
Interrupt(3) -- Receive FIFO Full
This interrupt is set when the Receive FIFO Programmable Depth Interrupt Register (Rc_FIFO_PIRQ) is equal to the
Receive FIFO Occupancy Register (Rc_FIFO_OCY). Clearing this interrupt requires that the Data Receive FIFO be
read.
Interrupt(4) -- IIC Bus is Not Busy
Interrupt(4) is set when the IIC bus is not busy. The condition remains set as long as the bus is not busy and cannot
be cleared while the condition is true. Firmware must verify that the SR(BB) is asserted, indicating Bus Busy, before
attempting to reset this interrupt bit.
A master that looses arbitration will want to get back on the bus (possibly) when it goes free. So it must immediately
clear this bit in anticipation of that occurring.
If necessary, the slave should clear this bit after getting the AAS interrupt to know when the bus is not busy occurs.
(A master could talk to several slaves before relinquishing the bus.)
Interrupt(5) -- Addressed As Slave
This interrupt is set when the XPS IIC is being addressed as a slave.
Interrupt(6) -- Not Addressed As Slave
This interrupt allows the detection of the end of receive data for a slave receiver when there has been no stop
condition (repeated start). The interrupt occurs when a start condition followed by a non-matching slave address is
detected. This interrupt is set when the IIC is not addressed as a slave.
Interrupt(7) -- Transmit FIFO Half Empty
This interrupt is set while the MSB of the Tx_FIFO_OCY = 0.
Throttle Description
The Philips I²C-bus Specification permits devices to throttle (suspend) data transmission on the bus by holding the
SCL line low for an indefinite period of time. The XPS IIC controller uses this throttling mechanism to prevent
either a receive overrun (Rx_FIFO full) or a transmit underflow (Tx_FIFO empty) by holding the SCL line low after
the acknowledge bit has been sent.
DS606 June 22, 2011
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Product Specification