DS606 Datasheet, PDF (24/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
IIC Master Receiver, with a repeated start
1. Write the IIC peripheral device addresses for the first slave device to the Tx_FIFO. Write the Receive FIFO
Programmable Depth Interrupt Register (Rc_FIFO_PIRQ) to the total message length (call it M) minus two. It is
assume that the message is less than the maximum FIFO depth of 16 bytes.
2. Set Control Register (CR) MSMS = 1 and Control Register (CR) TX = 0.
3. Wait for the Receive FIFO interrupt indicating M-1 bytes have been received.
4. Set Control Register (CR) TXAK = 1.
TXAK causes the XPS IIC controller to not-acknowledge the next byte received indicating to the slave
transmitter that the master receiver will accept no further data. TXAK is set before reading data from the
Rc_FIFO, because as soon as a read from the Rc_FIFO has occurred, the throttle condition is removed and the
opportunity to set the bit is lost.
5. Read all M-1 data bytes from the Rc_FIFO. Set the Rc_FIFO_PIRQ to 0 so that the last byte, soon to be received,
causes the Receive FIFO full interrupt to be raised.
6. Clear the Receive FIFO full interrupt now because after a single byte is retrieved from the Rc_FIFO the throttle
condition is removed by the controller and the interrupt flag can be lowered (cleared).
7. Wait for the Receive FIFO full interrupt.
8. The controller will be throttled again with a full Rc_FIFO. Set Control Register (CR) RSTA = 1. Write the
peripheral IIC device address for a new (or same) IIC slave to the Tx_FIFO.
9. Read the final byte of data (of the first message) from the Rc_FIFO. This terminates the throttle condition so the
Receive FIFO full interrupt can be cleared at this time. It also permits the controller to issue the IIC restart and
transmit the new slave address available in the Tx_FIFO. Also set the Rc_FIFO_PIRQ to be 2 less then the total
2nd message length (call it N) in anticipation of receiving the message of N-1 bytes from the second slave
device.
10. Wait for the Receive FIFO full interrupt.
11. Set TXAK = 1. Write the Rc_FIFO_PIRQ to be 0, read the message from the Rc_FIFO and clear the Receive FIFO
full interrupt.
12. Wait for the Receive FIFO full interrupt (signalling the last byte is received).
13. Set MSMS = 0 in anticipation of giving up the bus via generation of an IIC Stop.
14. Read the final data byte of the second message from the Rc_FIFO. This clears the throttle condition and makes
way for the controller to issue the IIC Stop.
IIC Slave Receiver
1. Set Control Register (CR) EN = 1 to enable the XPS IIC. If the IIC needs to recognize a general call then set EN
= 1 and GC_EN = 1.
2. Write the Slave address and R/W bit to the Slave Address Register (ADR). In seven bit mode, a slave address of
0x7F should be written as 0xFE to the ADR. The 8^th bit is the Read Not Write bit which is 0 in the case of a master
transmit (IE Write) to slave. S0, 111 1111 0 = FE.
3. Write 0x0 to the Receive FIFO Programmable Depth Interrupt Register (Rc_FIFO_PIRQ) Compare Value. That
causes an interrupt when 1 byte of data (not address) has been received. Because the address transmitted on the
IIC bus is not stored in the receive FIFO, this interrupt will not be caused by receiving either a seven bit address
or a ten bit address.
4. Wait for addressed as slave interrupt AAS.
5. Once an AAS interrupt has occurred, determine if the IIC slave is to receive or transmit data by reading Status
Register bit 4
6. Clear not addressed as slave interrupt NAS.
7. If the IIC is a slave receiver, there are two basic choices for the slave receiver interrupt processing.
DS606 June 22, 2011
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Product Specification