DS606 Datasheet, PDF (4/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Table 1: XPS IIC Design Parameters (Cont’d)
Generic Feature / Description Parameter Name
Allowable Values
G9 10 Bit Addressing
C_TEN_BIT_ADR
1 = The slave responds to 10 bit
addresses
0 = The slave responds to 7 bit
addresses
G10 Width of GPO
C_GPO_WIDTH
1 to 8
G11
SPLB Clock Frequency
(Hz)
C_CLK_FREQ
See Allowable Parameter
Combinations
G12 SCL filtering
C_SCL_INERTIAL_DE
LAY
0-255⁽⁴⁾
G13 SDA filtering
C_SDA_INERTIAL_DE
LAY
0-255
Default
Value
VHDL
Type
0
integer
1
25E6
0
0
integer
integer
integer
integer
Notes:
1. Address range specified by C_BASEADDR and C_HIGHADDR must be at least 0x200 and must be a power of 2.
2. No default value will be specified to insure that the actual value is set, i.e. if the value is not set, a compiler error will be generated.
3. The XPS IIC will only meet this frequency exactly when C_IIC_FREQ divides evenly into C_CLK_FREQ.
4. A value of 0 indicates that no filtering is applied to the given signal.
Parameter Description
C_IIC_FREQ
This parameter determines the approximate frequency of the master mode generated SCL clock signal (Hz). For
C_IIC_FREQ <= 100,000 the appropriate timing specifications for standard mode operation are used. For
C_IIC_FREQ > 100,000 the specifications for fast mode operation are used. See the Philips I²C-bus Specification,
Version 2.1, January 2000 for details.
Note:
1. The actual measure SCL clock may vary from the value specified in the C_IIC_FREQ parameter for a number of reasons. In
particular low period and high period of the clock are determined by counting off system clocks from the moment the SCL
signal is sampled low or sampled high. As a result, the rise and fall time of the signals will affect the SCL clock frequency.
2. The C_IIC_FREQ does not equate to the data bandwidth in bps. Overhead in transmitting START, STOP and addresses
reduces the effective bandwidth below the line rate.
3. IIC slaves may also control the clock rate to throttle data transfers to a manageable speed thus changing the effective SCL
clock rate.
4. The actual frequency will only match the specified value when C_CLK_FREQ is an integer multiple of C_IIC_FREQ.
C_TEN_BIT_ADR
This parameter enables or disables the 10-bit addressing mode. Logic resource savings result when 10-bit
addressing is disabled.
C_GPO_WIDTH
This parameter sets the width of the general purpose output vector. If the user does not connect anything to this
port, then logic optimization will remove any resources associated with it.
C_CLK_FREQ
This parameter specifies (but does not set) the frequency of the PLB bus. The XPS IIC utilizes the SPLB_CLK for its
system clock and it must know the ratio of the C_IIC_FREQ to the C_CLK_FREQ to meet IIC timing specifications.
DS606 June 22, 2011
www.xilinx.com
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Product Specification