DS606 Datasheet, PDF (6/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
C_FAMILY
This parameter is defined as a string. It specifies the target FPGA technology for implementation of the PLB Slave.
This parameter is required for proper selection of FPGA primitives. The configuration of these primitives can vary
from one FPGA technology family to another.
Allowable Parameter Combinations
Because of the pipelined design of the XPS IIC, the PLB bus clock frequency must be at least 25 MHz and 25 times
faster than the SCL clock frequency.
I/O Signals
The I/O signals for the XPS IIC are listed and described in Table 2.
Table 2: XPS IIC I/O Signal Description
Port
Signal Name
Interface
I/O
Initial
State
Description
P1 SPLB_Clk
P2 SPLB_Rst
P3 IIC2INTC_Irpt
P4 PLB_ABus[0 : 31]
P5 PLB_PAValid
P6
PLB_masterID[0:C_SPLB_
MID_WIDTH - 1]
P7 PLB_RNW
P8
PLB_BE[0 :
[C_SPLB_DWIDTH/8] - 1]
P9 PLB_size[0 : 3]
P10 PLB_type[0 : 2]
P11
PLB_wrDBus[0 :C_SPLB_
DWIDTH - 1]
P13 PLB_UABus[0 : 31]
P14 PLB_SAValid
P15 PLB_rdPrim
P16 PLB_wrPrim
P17 PLB_abort
P18 PLB_busLock
P19 PLB_MSize[0 : 1]
P20 PLB_TAttribute[0 : 15]
P21 PLB_lockerr
P22 PLB_wrBurst
System Signals
PLB Bus
I
- PLB bus clock
PLB Bus
I
- PLB bus reset
System
O
0 System Interrupt output
PLB Master Interface Signals
PLB
I
- PLB address bus
PLB
I
- PLB primary address valid indicator
PLB
I
- PLB current master identifier
PLB
I
- PLB read not write
PLB
I
- PLB byte enables
PLB
I
- PLB transfer size
PLB
I
- PLB transfer type
PLB
I
- PLB write data bus
Unused PLB Master Interface Signals
PLB
I
- PLB upper address bits
PLB
I
- PLB secondary address valid
PLB
I
- PLB secondary to primary read request indicator
PLB
I
- PLB secondary to primary write request indicator
PLB
I
- PLB abort bus request
PLB
I
- PLB bus lock
PLB
I
- PLB data bus width indicator
PLB
I
- PLB transfer attribute
PLB
I
- PLB lock error
PLB
I
- PLB burst write transfer
DS606 June 22, 2011
www.xilinx.com
6
Product Specification