DS606 Datasheet, PDF (16/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Status Register (SR)
This register contains the status of the XPS IIC Bus Interface. The read-only SR register is shown in Figure 7 and
described in Table 10. All bits are cleared upon reset.
Figure Top x-ref 7
Rc_Fifo Tx_Fifo
_Empty _Full BB ABGC
0
23 24 25 26 27 28 29 30 31
Reserved
Tx_Fifo Rc_Fifo SRW AAS
_Empty _Full
Figure 7: Status Register (SR)
Table 10: Status Register (C_BASEADDR + 0x104)
Bit(s)
Name
Core
Access
Reset
Value
Description
0- 23
Reserved
N/A
N/A Reserved
24
Tx_FIFO_Empty
Read
1
Transmit FIFO empty. This bit is set High when the transmit FIFO
is empty.
25
Rc_FIFO_Empty
Read
1
Receive FIFO empty. This is set High when the receive FIFO is
empty.
26
Rc_FIFO_Full
Read
Receive FIFO full. This bit is set High when the receive FIFO is
0
full. This bit is set only when all sixteen locations in the FIFO are
full, regardless of the compare value field of the Rc_FIFO_PIRQ
register.
27
Tx_FIFO_Full
Read
0
Transmit FIFO full. This bit is set High when the transmit FIFO is
full.
Slave Read/Write. When the IIC Bus Interface has been
addressed as a Slave (AAS is set), this bit indicates the value of
the read/write bit sent by the Master. This bit is only valid when a
28
SRW
Read
0
complete transfer has occurred and no other transfers have been
initiated.
“1” indicates Master reading from Slave.
“0” indicates Master writing to Slave.
Bus Busy. This bit indicates the status of the IIC bus. This bit is
set when a START condition is detected and cleared when a
29
BB
Read
0
STOP condition is detected.
“1” indicates the bus is busy.
“0” indicates the bus is idle.
Addressed as Slave. When the address on the IIC bus matches
the Slave address in the Address Register (ADR), the IIC Bus
Interface is being addressed as a Slave and switches to Slave
mode. If 10-bit addressing is selected this device will only respond
30
AAS
Read
0
to a 10-bit address or general call if enabled. This bit is cleared
when a stop condition is detected or a repeated start occurs.
“1” indicates being addressed as a slave.
“0” indicates not being addressed as a slave.
Addressed By a General Call. This bit is set high when another
31
ABGC
Read
0
master has issued a general call and the general call enable bit is
set high, CR(25) = ’1’.
DS606 June 22, 2011
www.xilinx.com
16
Product Specification