DS606 Datasheet, PDF (21/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
The GPO register is shown in Figure 15 and described in Table 18.
Figure Top x-ref 15
General Purpose Output
0
A
31
Reserved
A = (32-C_GPO_WIDTH)
Figure 15: General Purpose Output Register (GPO)
Table 18: General Purpose Output Register (C_BASEADDR + 0x124)
Bit(s)
Name
Access
Reset
Value
Description
0 - (31-C_GPO_WIDTH) Reserved
N/A
N/A Reserved
(32-C_GPO_WIDTH) - 31
General Purpose
Outputs
Read/Write
0x0 GPO - The LSB (bit 31) is the first bit populated.
XPS IIC Interrupt Descriptions
The XPS IIC driver firmware has eight unique interrupts available to manage IIC data transfers. The interrupt
signals generated by the XPS IIC’s internal IIC control module are managed by the Interrupt Control (v2.01a) block.
The registers within this block provide an interface containing many of the features commonly needed for interrupt
handling.
Interrupt(0) -- Arbitration Lost
Interrupt(0) is the Arbitration Lost interrupt. This interrupt is set when arbitration for the IIC bus is lost. The
firmware must respond by first clearing the Control Register (CR) MSMS bit then second clearing this interrupt by
writing a 1 to the Interrupt Status Register (ISR) INT(0) bit to toggle it. See also: Tx_FIFO reset bit in the Control
Register (CR).
Interrupt(1) -- Transmit Error/Slave Transmit Complete
There are four possible events that cause this interrupt:
• XPS IIC operating as a Master Transmitter: Interrupt(1) implies an error. There are two possibilities: A) Either no
slave was present at the transmitted address in which case the master transmitter recognizes a NOT
ACKNOWLEDGE. B) The slave receiver issued a NOT ACKNOWLEDGE to signal that it is not accepting any
more data. In either case the MSMS bit in the Control Register will transition from 1 to 0 causing the XPS IIC to
initiate a stop condition which implies that the bus will not be busy.
• XPS IIC operating as a Master Receiver: Interrupt(1) implies a transmit complete. This interrupt is caused by
setting Control Register (CR) TXAK high to indicate to the slave transmitter that the last byte has been
transmitted.
• XPS IIC operating as a Slave Transmitter: Interrupt(1) implies a transmit complete. This interrupt is caused by
the master device to indicate to the IIC that the last byte has been transmitted.
• XPS IIC operating as a Slave Receiver: Interrupt(1) implies an error. This interrupt is caused by the IIC (setting
CR register field TXAK to 1).
DS606 June 22, 2011
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Product Specification