DS606 Datasheet, PDF (12/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Global Interrupt Enable (GIE)
The Global Interrupt Enable Register, illustrated in Figure 3, and described in Table 5, has a single defined bit, in the
most significant bit that is used to globally enable the final interrupt (coalesced from the ISR) out to the system.
Figure Top x-ref 3
01
31
GIE
Reserved
Figure 3: Global Interrupt Enable (GIE) Register
Table 5: Global Interrupt Enable (GIE) Register (C_BASEADDR + 0x01C)
Bit(s)
Name
Core Access
Reset
Value
Description
Global Interrupt Enable.
0
GIE
Read/Write
0
0 = All Interrupts disabled; no interrupt (even if unmasked in IER)
possible from XPS IIC.
1 = Unmasked XPS IIC interrupts are passed to processor.
1-31
Reserved
N/A
N/A Reserved
Interrupt Status Register (ISR)
Firmware uses the ISR to determine which interrupt events from the XPS IIC need servicing. The register uses a
toggle on write method to allow the firmware to easily clear selected interrupts by writing a ’1’ to the desired
interrupt bit field position.This mechanism avoids the requirement on the User Interrupt Service routine to perform
a Read/Modify/Write operation to clear a single bit within the register. Note that an interrupt value of ’1’ means the
interrupt has occurred. A value of zero means that no interrupt occurred or it was cleared.
Table 6 illustrates the interrupt to bit field mappings of the IPIER (interrupt enable) and IPISR (interrupt status)
registers. The number in the parenthesis is the interrupt bit number.
Figure Top x-ref 4
Not Addressed
Tx FIFO
as Slave Int(6) Empty Int(2) _Arb
Bus Not
Lost
Busy Int (4)
Int (0)
0
23 24 25 26 27 28 29 30 31
Reserved
Addressed Tx Error Slave
as Slave (Int5) Tx Comp (Int1)
Tx Fifo
Rc FIFO
Half Empty
Full (Int3)
Int (7)
Figure 4: Interrupt Status Register (ISR)
DS606 June 22, 2011
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Product Specification