DS606 Datasheet, PDF (32/32 Pages) Xilinx, Inc – Multi-master operation

XPS IIC Bus Interface (v2.03a)
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Reference Documents
• IBM CoreConnect™ 128-Bit Processor Local Bus, Architectural Specification (v4.6)
• Philips I2C-bus Specification, Version 2.1, January 2000
• Xilinx Interrupt Control Design Specification(DS516)
• Xilinx PLBV46 Slave Single Design Specification(DS565)
Revision History
Date
7/24/07
10/1/07
12/3/07
4/16/08
7/22/08
1/28/09
4/24/09
6/16/09
12/02/09
01/04/10
04/19/10
6/22/11
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
Revision
Initial Xilinx release.
Added FMax Margin System Performance section.
Updated to V2.00a core revision.
Added information about the new C_SCL/SDA_INERTIAL_DELAY parameters used to
determine the amount of pulse rejection filtering.
Added Automotive Spartan-3, Automotive Spartan-3E, Automotive Spartan-3A, and
Automotive Spartan-3A DSP support.
Added QPro Virtex-4 Hi-Rel and QPro Virtex-4 Rad Tolerant FPGA support.
Updated to v2.01.a core revision.
Removed Virtex2p support.
Replaced references to supported device families and tool name(s) with hyperlink to PDF file.
Updated performance and resource utilization table for V6 and S6 architecture.
Updated to v2.02.a.
Updated to v2.03.a.
Updated resource utilization and Fmax system diagrams from V6 and S6 family.
Updated to 13.2; incorporated CR588647.
DS606 June 22, 2011
www.xilinx.com
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Product Specification