XC3000FM Datasheet, PDF (8/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
A
B
QX
QY
C
D
E
A
B
QX
QY
C
D
E
Any Function
of Up to 4
F
Variables
Any Function
of Up to 4
Variables
G
5a
A
B
QX
QY
C
D
E
Any Function
of 5 Variables
F
G
5b
A
B
QX
QY
C
D
A
B
QX
QY
C
D
E
Figure 5
Any Function
of Up to 4
Variables
Any Function
of Up to 4
Variables
F
M
U
X
G
FGM
5c _Mode
X5442
5a. Combinatorial Logic Option FG generates two functions
of four variables each. One variable, A, must be common
to both functions. The second and third variable can be
any choice of of B, C, QX and QY The fourth variable
can be any choice of D or E.
5b. Combinatorial Logic Option F generates any function of
five variables: A, D, E and and two choices out of B, C,
QX, QY.
5c. Combinatorial Logic Option FGM allows variable E to
select between two functions of four variables: Both have
common inputs A and D and any choice out of B, C, QX
and QY for the remaining two variables. Option 3 can
then implement some functions of six or seven variables.
Count Enable
Parallel Enable
Clock
D0
Dual Function of 4 Variables
Terminal
Count
DQ
Q0
FG
Mode
DQ
Q1
D1
Function of 5 Variables
F
Mode
DQ
Q2
D2
Function of 6 Variables
FGM
Mode
X5383
Figure 6. C8BCP Macro.
The C8BCP macro (modulo-8 binary counter with parallel
enable and clock enable) uses one combinatorial logic block
of each option.
2-110