XC3000FM Datasheet, PDF (7/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

Configurable Logic Block
The array of CLBs provides the functional elements from
which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. The
XC3020 has 64 such blocks arranged in 8 rows and 8
columns. The XACT development system is used to com-
pile the configuration data which is to be loaded into the
internal configuration memory to define the operation and
interconnection of each block. User definition of CLBs and
their interconnecting networks may be done by automatic
translation from a schematic-capture logic diagram or
optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 4. There are:
five logic inputs (A, B, C, D and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from
the function F or G outputs of the combinatorial logic, or the
block input, DI. Both flip-flops in each CLB share the
DI
DATA IN
A
B
LOGIC
C
VARIABLES
D
E
QX
F
COMBINATORIAL
FUNCTION
G
QY
0
MUX
DQ
F
1
DIN
G
RD
QX
X
F
CLB OUTPUTS
G
Y
F
QY
DIN
G
0
MUX
DQ
1
EC
ENABLE CLOCK
RD
1 (ENABLE)
K
CLOCK
DIRECT
RD
RESET
0 (INHIBIT)
(GLOBAL RESET)
Figure 4. Configurable Logic Block. Each CLB includes a combinatorial logic section, two flip-flops and a program
memory controlled multiplexer selection of function. It has. five logic variable inputs A, B, C, D, and E
a direct data in DI
an enable clock EC
a clock (invertible) K
an asynchronous direct RESET RD
two outputs X and Y
X3032
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