XC3000FM Datasheet, PDF (42/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
XC3000 Families 132-Pin Ceramic and Plastic PGA Pinouts
XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts
PGA Pin
Number
C4
A1
C3
B2
B3
A2
B4
C5
A3
A4
B5
C6
A5
B6
A6
B7
C7
C8
A7
B8
A8
A9
B9
C9
A10
B10
A11
C10
B11
A12
B12
A13
C12
XC3042
XC3064
GND
PWRDN
I/O-TCLKIN
I/O
I/O
I/O*
I/O
I/O
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O*
I/O
I/O
I/O*
I/O
I/O*
I/O
PGA Pin
Number
B13
C11
A14
D12
C13
B14
C14
E12
D13
D14
E13
F12
E14
F13
F14
G13
G14
G12
H12
H14
H13
J14
J13
K14
J12
K13
L14
L13
K12
M14
N14
M13
L12
XC3042
XC3064
M1-RD
GND
M0-RT
VCC
M2-I/O
HDC-I/O
I/O
I/O
I/O
LDC-I/O
I/O*
I/O
I/O
I/O
I/O
I/O
INIT-I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O*
I/O
I/O
I/O
I/O
XTL2(IN)-I/O
GND
PGA Pin
Number
P14
M11
N13
M12
P13
N12
P12
N11
M10
P11
N10
P10
M9
N9
P9
P8
N8
P7
M8
M7
N7
P6
N6
P5
M6
N5
P4
P3
M5
N4
P2
N3
N2
XC3042
XC3064
RESET
VCC
DONE-PG
D7-I/O
XTL1-I/O-BCLKIN
I/O
I/O
D6-I/O
I/O
I/O*
I/O
I/O
D5-I/O
CS0-I/O
I/O*
I/O*
D4-I/O
I/O
VCC
GND
D3-I/O
CS1-I/O
I/O*
I/O*
D2-I/O
I/O
I/O
I/O
D1-I/O
RDY/BUSY-RCLK-I/O
I/O
I/O
D0-DIN-I/O
PGA Pin
Number
M3
P1
M4
L3
M2
N1
M1
K3
L2
L1
K2
J3
K1
J2
J1
H1
H2
H3
G3
G2
G1
F1
F2
E1
F3
E2
D1
D2
E3
C1
B1
C2
D3
XC3042
XC3064
DOUT-I/O
CCLK
VCC
GND
A0-WS-I/O
A1-CS2-I/O
I/O
I/O
A2-I/O
A3-I/O
I/O
I/O
A15-I/O
A4-I/O
I/O*
A14-I/O
A5-I/O
GND
VCC
A13-I/O
A6-I/O
I/O*
A12-I/O
A7-I/O
I/O
I/O
A11-I/O
A8-I/O
I/O
I/O
A10-I/O
A9-I/O
VCC
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed
outputs are default slew-rate limited.
* Indicates unconnected package pins (14) for the XC3042.
2-144