XC3000FM Datasheet, PDF (29/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

Slave Serial Mode Programming Switching Characteristics
DIN
CCLK
DOUT
(Output)
CCLK
Bit n
1 T_DCC
2 T_CCD
Bit n + 1
5 T_CCL
4 T_CCH
Bit n - 1
3 T_CCO
Description
To DOUT
DIN setup
DIN hold
High time
Low time (Note 1)
Frequency
Symbol
3 T_CCO
1 T_DCC
2 T_CCD
4 T_CCH
5 T_CCL
F_CC
Min
60
0
0.05
0.05
Bit n
X5379
Max
100
5.0
10
Units
ns
ns
ns
µs
µs
MHz
Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the LCA device.
2. Configuration must be delayed until the INIT of all LCA devices is High.
3. At power-up, V_CC must rise from 2.0 V to V_CC min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RESET Low until V_CC has reached 4.0 V (2.5 V for the XC3000L). A very long V_CC rise time of >100
ms, or a non-monotonically rising V_CC may require a >6-µs High level on RESET, followed by a >6-µs Low level on
RESET and D/P after V_CC has reached 4.0 V (2.5 V for the XC3000L).
Program Readback Switching Characteristics
DONE/PROG
(OUTPUT)
RTRIG (M0)
1 T_RTH
CCLK(1)
M1 Input/
RDATA Output
4 T_CCL
3 T_CCRD
H1-Z
2 _TRTCC
5
4 _TCCL
VALID
READBACK OUTPUT
RTRIG
CCLK
Description
RTRIG High
RTRIG setup
RDATA delay
High time
Low time
Symbol
1 T_RTH
2 T_RTCC
3 T_CCRD
5 T_CCHR
4 T_CCLR
VALID
READBACK OUTPUT
X6116
Min
Max
250
200
100
0.5
0.5
5
Units
ns
ns
ns
µs
µs
Notes: 1. During Readback, CCLK frequency may not exceed 1 MHz.
2. RETRIG (M0 positive transition) shall not be done until after one clock following active I/O pins.
3. Readback should not be initiated until configuration is complete.
4. T_CCLR is 5 µs min to 15 µs max for XC3000L.
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