XC3000FM Datasheet, PDF (39/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000 Families 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts
XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts
68 PLCC
XC3030
10
11
12
13
14
—
15
16
—
17
18
19
—
20
—
21
22
23
24
25
26
27
28
29
30
—
—
31
32
33
34
35
36
37
38
39
—
—
40
41
42
43
XC3020
10
11
—
12
13
—
14
15
16
17
18
19
—
20
21
22
—
23
24
25
26
27
28
29
30
31
32
33
—
34
35
36
37
38
39
40
41
42
43
XC3020
XC3030, XC3042
PWRDN
TCLKIN-I/O
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1-RDATA
M0-RTRIG
M2-I/O
HDC-I/O
I/O
LDC-I/O
I/O
I/O*
I/O
I/O
I/O*
INIT-I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O*
I/O*
I/O
XTL2(IN)-I/O
84 PLCC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
84 PGA
B2
C2
B1
C1
D2
D1
E3
E2
E1
F2
F3
G3
G1
G2
F1
H1
H2
J1
K1
J2
L1
K2
K3
L2
L3
K4
L4
J5
K5
L5
K6
J6
J7
L7
K7
L6
L8
K8
L9
L10
K9
L11
68 PLCC
XC3030
XC3020
44
45
46
47
48
—
49
50
51
—
52
53
54
55
—
—
56
57
58
59
60
61
62
63
64
—
—
65
66
67
68
1
2
3
4
5
—
—
6
7
8
9
XC3020
XC3030, XC3042
RESET
DONE-PG
D7-I/O
XTL1(OUT)-BCLKIN-I/O
D6-I/O
I/O
D5-I/O
CS0-I/O
D4-I/O
I/O
VCC
D3-I/O
CS1-I/O
D2-I/O
I/O
I/O*
D1-I/O
RDY/BUSY-RCLK-I/O
D0-DIN-I/O
DOUT-I/O
CCLK
A0-WS-I/O
A1-CS2-I/O
A2-I/O
A3-I/O
I/O*
I/O*
A15-I/O
A4-I/O
A14-I/O
A5-I/O
GND
A13-I/O
A6-I/O
A12-I/O
A7-I/O
I/O*
I/O*
A11-I/O
A8-I/O
A10-I/O
A9-I/O
84 PLCC
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
2
3
4
5
6
7
8
9
10
11
84 PGA
K10
J10
K11
J11
H10
H11
F10
G10
G11
G9
F9
F11
E11
E10
E9
D11
D10
C11
B11
C10
A11
B10
B9
A10
A9
B8
A8
B6
B7
A7
C7
C6
A6
A5
B5
C5
A4
B4
A3
A2
B3
A1
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed
outputs are default slew-rate limited.
This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the 118
pads on the XC3042 (and 84 of the 98 pads on the XC3030) that are connected to the 84 package pins. Ten pads, indicated by an
asterisk, do not exist on the XC3020, which has 74 pads; therefore the corresponding pins on the 84-pin packages have no
connections to an XC3020. Six pads on the XC3020 and 16 pads on the XC3030, indicated by a dash (—) in the 68 PLCC column,
have no connection to the 68 PLCC, but are connected to the 84-pin packages.
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