XC3000FM Datasheet, PDF (4/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
The XC3000 Logic Cell Array families provide a variety of
logic capacities, package styles, temperature ranges and
speed grades.
Architecture
The perimeter of configurable IOBs provides a pro-
grammable interface between the internal logic array and
the device package pins. The array of CLBs performs
user-specified logic functions. The interconnect resources
are programmed to form networks, carrying logic signals
among blocks, analogous to printed circuit board traces
connecting MSI/SSI packages.
The block logic functions are implemented by programmed
look-up tables. Functional options are implemented by
program-controlled multiplexers. Interconnecting networks
between blocks are implemented with metal segments
joined by program-controlled pass transistors.
These LCA functions are established by a configuration
program which is loaded into an internal, distributed array
of configuration memory cells. The configuration program
is loaded into the LCA device at power-up and may be
reloaded on command. The Logic Cell Array includes logic
and control signals to implement automatic or passive
configuration. Program data may be either bit serial or byte
parallel. The XACT development system generates the
configuration program bitstream used to configure the
LCA device. The memory loading process is independent
of the user logic functions.
Configuration Memory
The static memory cell used for the configuration memory
in the Logic Cell Array has been designed specifically for
high reliability and noise immunity. Integrity of the LCA
device configuration memory based on this design is
assured even under adverse conditions. Compared with
other programming alternatives, static memory provides
the best combination of high density, high performance,
high reliability and comprehensive testability. As shown in
Figure 2, the basic memory cell consists of two CMOS
inverters plus a pass transistor used for writing and read-
ing cell data. The cell is only written during configuration
and only read during readback. During normal operation,
the cell provides continuous control and the pass transistor
is off and does not affect cell stability. This is quite different
from the operation of conventional memory devices, in
which the cells are frequently read and rewritten.
PWR
DN
P9
P8
I/O Blocks
P7
P6
P11
3-State Buffers With Access
to Horizontal Long Lines
TCL
KIN
AA
AB
P12
P5
P4
P3
P2
GND
Configurable Logic
Blocks
AC
AD
Interconnect Area
P13
BA
BB
U61
Configuration Memory
Figure 1. Logic Cell Array Structure.
X3241
It consists of a perimeter of programmable I/O blocks, a core of configurable logic blocks and their interconnect resources.
These are all controlled by the distributed array of configuration program memory cells.
2-106