XC3000FM Datasheet, PDF (40/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
XC3064/XC3090/XC3195 84-Pin PLCC Pinouts
XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts
PLCC
Pin Number
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
XC3064, XC3090, XC3195
PWRDN
TCLKIN-I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNDI
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1-RDATA
M0-RTRIG
M2-I/O
HDC-I/O
I/O
LDC-I/O
I/O
I/O
I/O
I/O
INIT/I/OI
VCCI
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XTL2(IN)-I/O
PLCC
Pin Number
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
2
3
4
5
6
7
8
9
10
11
XC3064, XC3090, XC3195
RESET
DONE-PG
D7-I/O
XTL1(OUT)-BCLKIN-I/O
D6-I/O
I/O
D5-I/O
CS0-I/O
D4-I/O
I/O
VCC
GNDI
D3-I/OI
CS1-I/OI
D2-I/OI
I/O
D1-I/O
RDY/BUSY-RCLK-I/O
D0-DIN-I/O
DOUT-I/O
CCLK
A0-WS-I/O
A1-CS2-I/O
A2-I/O
A3-I/O
I/O
I/O
A15-I/O
A4-I/O
A14-I/O
A5-I/O
GND
VCCI
A13-I/OI
A6-I/OI
A12-I/OI
A7-I/OI
I/O
A11-I/O
A8-I/O
A10-I/O
A9-I/O
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed
ouptuts are default slew-rate limited.
I _{In the PC84 package, XC3064, XC3090 and XC3195 have additional VCC and GND pins and thus a different pin definition than}
XC3020/XC3030/XC3042.
2-142