XC3000FM Datasheet, PDF (16/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
DQ
Internal External
Alternate
Clock Buffer
XTAL1
XTAL2
(IN)
Suggested Component Values
R1 0.5 – 1 MΩ
R2 0 – 1 kΩ
(may be required for low frequency, phase)t
(shift and/or compensation level for crystal Q)
C1, C2 10 – 40 pF
Y1 1 – 20 MHz AT-cut parallel resonant
Y1
C1
R1
R2
C2
XTAL 1 (OUT)
XTAL 2 (IN)
44 PIN
PLCC
30
26
68 PIN
PLCC
47
43
84 PIN
PLCC PGA
57
J11
53
L11
100 PIN
CQFP PQFP
67
82
61
76
132 PIN
PGA
P13
M13
160 PIN
PQFP
82
76
164 PIN
CQFP
105
99
175 PIN 208 PIN
PGA PQFP
T14
110
P15
100
X5302
Figure 17. Crystal Oscillator Inverter. When activated in the MakeBits program and by selecting an output network for its buffer,
the crystal oscillator inverter uses two unconfigured package pins and external components to implement an oscillator. An optional
divide-by-two mode is available to assure symmetry.
resistance. Crystal oscillators above 20 MHz generally
require a crystal which operates in a third overtone mode,
where the fundamental frequency must be suppressed by
an inductor across C2, turning this parallel resonant circuit
to double the fundamental crystal frequency, i.e., 2/3 of the
desired third harmonic frequency network. When the oscil-
lator inverter is not used, these IOBs and their package
pins are available for general user I/O.
Programming
Table 1
M0 M1 M2 CCLK Mode
Data
0 0 0 output Master Bit Serial
0 0 1 output Master Byte Wide Addr. = 0000 up
0 10—
reserved —
0 1 1 output Master Byte Wide Addr. = FFFF
down
1 00—
reserved —
1 0 1 output Peripheral Byte Wide
1 10—
reserved —
1 1 1 input Slave
Bit Serial
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. When Vcc reaches the voltage at which portions
of the LCA device begin to operate (nominally 2.5 to 3 V),
the programmable I/O output buffers are 3-stated and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allow the power
supply voltage to stabilize. During this time the power-
down mode is inhibited. The Initialization state time-out
(about 11 to 33 ms) is determined by a 14-bit counter
driven by a self-generated internal timer. This nominal 1-
MHz timer is subject to variations with process, tempera-
ture and power supply. As shown in Table 1, five configu-
ration mode choices are available as determined by the
input levels of three mode pins; M0, M1 and M2.
In Master configuration modes, the LCA device becomes
the source of the Configuration Clock (CCLK). The begin-
ning of configuration of devices using Peripheral or Slave
modes must be delayed long enough for their initialization
to be completed. An LCA device with mode lines selecting
a Master configuration mode extends its initialization state
using four times the delay (43 to 130 ms) to assure that all
daisy-chained slave devices, which it may be driving, will
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