XC3000FM Datasheet, PDF (50/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
For a detailed description of the device architecture, see pages 2-105 through 2-123.
For a detailed description of the configuration modes and their timing, see pages 2-124 through 2-132.
For detailed lists of package pin-outs, see pages 2-140 through 2-150.
For package physical dimensions and thermal data, see Section 4.
Ordering Information
Example:
Device Type
XC3130A- 3 PC44C
Temperature Range
Block Delay
Number of Pins
XC3000, XC3000A, XC3000L, XC3100, XC3100A
The features of the original XC3000 family are described
on the preceding pages.
XC3100A is functionally identical with XC3000, but offers
substantially faster performance. There is also an addi-
tional high-end family member, the XC3195A.
XC3000L uses a 3.3 V supply voltage and has lower
power-down current.
The XC3000A, XC3000L and XC3100A families all offer
identical enhanced functionality. They are thus supersets
of the XC3000 familiy.
Additional routing resources provide improved perfor-
mance and higher density. There is now a direct connec-
tion from each CLB output to the data input of its nearest
TBUF. This speeds up the path and preserves general
routing resources that can be used for other purposes.
The CLB clock enable and the TBUF output enable are
now driven by two different vertical Longlines. In the
XC3000/3100 devices, the CLB clock enable signal and
the adjacent TBUF output enable signal can both be driven
only from the same vertical Longline. That makes these
two functions mutually exclusive, and thus creates place-
ment constraints. Using separate Longlines for these two
functions leads to improved density and performance,
especially in bus-oriented applications.
Bitstream error checking protects against erroneous
configuration.
Each Xilinx FPGA bitstream consists of a 40-bit preamble,
followed by a device-specific number of data frames. The
number of bits per frame is also device-specific; however,
each frame ends with three stop bits (111) followed by a
start bit for the next frame (0).
All devices in all XC3000 families start reading in a new
frame when they find the first 0 after the end of the previous
frame. XC3000/XC3100 devices do not check for the
correct stop bits, but XC3000A/XC3100A and XC3000L
devices check that the last three bits of any frame are
actually 111.
Under normal circumstances, all these FPGAs behave the
same way; however, if the bitstream is corrupted, an
Package Type
XC3000/XC3100 device will always start a new frame as
soon as it finds the first 0 after the end of the previous
frame, even if the data is completely wrong or out-of-sync.
Given sufficient zeros in the data stream, the device will
also go Done, but with incorrect configuration and the
possibility of internal contention.
An XC3000A/XC3100A/XC3000L device starts any new
frame only if the three preceding bits are all ones. If this
check fails, it pulls INIT Low and stops the internal configu-
ration, although the Master CCLK keeps running. The user
must then start a new configuration by applying a >6 µs
Low level on RESET.
This simple check does not protect against random bit
errors, but it offers almost 100 percent protection against
erroneous configuration files, defective configuration data
sources, synchronization errors between configuration
source and FPGA, or PC-board level defects, such as
broken lines or solder-bridges.
A separate modification slows down the RESET input
before configuration by using a two-stage shift register
driven from the internal clock. It tolerates submicrosecond
High spikes on RESET before configuration. The XC3000
master can be connected like an XC4000 master, but with
its RESET input used instead of INIT. (On XC3000, INIT is
output only).
Soft start-up. After configuration, the outputs of all LCA
device in a daisy-chain become active simultaneously, as
a result of the same CCLK edge. In the original XC3000/
3100 devices, each output becomes active in either fast or
slew-rate limited mode, depending on the way it is config-
ured. This can lead to large ground-bounce signals. In the
new XC3000A/XC3000L/XC31000A devices, all outputs
become active first in slew-rate limited mode, reducing the
ground bounce. After this soft start-up, each individual
output slew rate is again controlled by the respective
configuration bit.
The XC3000, XC3000L, ZC3100A are fully supported by
the XACT Version 5.0, or later, development system.
XACT 5.0 provides many advanced features not available
with the XC3000 software such as timing-driven place and
route (XACT-Performance™)and the X-BLOX™ module
generator.
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