XC3000FM Datasheet, PDF (34/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Pin Descriptions
Permanently Dedicated Pins.
V_CC
Two to eight (depending on package type) connections to
the positive V supply voltage. All must be connected.
GND
Two to eight (depending on package type) connections to
ground. All must be connected.
PWRDWN
A Low on this CMOS-compatible input stops all internal
activity, but retains configuration. All flip-flops and latches
are reset, all outputs are 3-stated, and all inputs are
interpreted as High, independent of their actual level.
When PWDWN returns High, the LCA device becomes
operational with DONE Low for two cycles of the internal
1-MHz clock.Before and during configuration, PWRDWN
must be High. If not used, PWRDWN must be tied to V_CC.
RESET
This is an active Low input which has three functions.
Prior to the start of configuration, a Low input will delay the
start of the configuration process. An internal circuit
senses the application of power and begins a minimal
time-out cycle. When the time-out and RESET are com-
plete, the levels of the M lines are sampled and configura-
tion begins.
If RESET is asserted during a configuration, the LCA
device is re-initialized and restarts the configuration at the
termination of RESET.
If RESET is asserted after configuration is complete, it
provides a global asynchronous RESET of all IOB and
CLB storage elements of the LCA device.
DONE/PROG (D/P)
DONE is an open-drain output, configurable with or without
an internal pull-up resistor of 2 to 8 k Ω. At the completion of
configuration, the LCA device circuitry becomes active in a
synchronous order; DONE is programmed to go active High
one cycle either before or after the outputs go active.
Once configuration is done, a High-to-Low transition of this
pin will cause an initialization of the LCA device and start
a reconfiguration.
M0/RTRIG
As Mode 0, this input is sampled on power-on to determine
the power-on delay (2¹⁴ cycles if M0 is High, 2¹⁶ cycles if
M0 is Low). Before the start of configuration, this input is
again sampled together with M1, M2 to determine the
configuration mode to be used .
A Low-to-High input transition, after configuration is com-
plete, acts as a Read Trigger and initiates a Readback of
configuration and storage-element data clocked by CCLK.
By selecting the appropriate Readback option when gen-
erating the bitstream, this operation may be limited to a
single Readback, or be inhibited altogether.
M1/RDATA
As Mode 1, this input and M0, M2 are sampled before the
start of configuration to establish the configuration mode to
be used. If Readback is never used, M1 can be tied directly
to ground or V_CC. If Readback is ever used, M1 must use
a 5-kΩ resistor to ground or V_CC, to accommodate the
RDATA output.
As an active-Low Read Data, after configuration is com-
plete, this pin is the output of the Readback data.
CCLK
During configuration, Configuration Clock is an output of
an LCA device in Master mode or Peripheral mode, but an
input in Slave mode. During Readback, CCLK is a clock
input for shifting configuration data out of the LCA device
CCLK drives dynamic circuitry inside the LCA device. The
Low time may, therefore, not exceed a few microseconds.
When used as an input, CCLK must be “parked High”. An
internal pull-up resistor maintains High when the pin is not
being driven.
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