XC3000FM Datasheet, PDF(48/50 Page) Xilinx, Inc – XC3000 Logic Cell Array Families

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XC3000FM Datasheet, PDF (48/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

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XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families

XC3195 PQ208 and PG223 Pinouts

Description

A9-I/O

A10-I/O

I/O

A8-I/O

A11-I/O

I/O

A7-I/O

A12-I/O

I/O

A6-I/O

A13-I/O

VCC

GND

I/O

A5-I/O

A14-I/O

I/O

A4-I/O

A15-I/O

I/O

A3-I/O

A2-I/O

I/O

A1-CS2-I/O

A0-WS-I/O

GND

VCC

CCLK

DOUT-I/O

PG223

PQ208 I

206

205

204

203

202

201

200

199

198

197

196

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

Description PG223 PQ208 I

I/O

U18

102

I/O

P15

101

I/O

T17

100

I/O

T18

I/O

P16

I/O

R17

I/O

N15

I/O

R18

I/O

P17

I/O

N17

I/O

N16

I/O

M15

I/O

M18

I/O

M17

I/O

L18

I/O

L17

I/O

L15

I/O

L16

I/O

K18

I/O

K17

I/O

K16

GND

K15

VCC

J15

INIT

J16

I/O

J17

I/O

J18

I/O

H16

I/O

H15

I/O

H17

I/O

H18

I/O

G17

I/O

G18

I/O

G15

I/O

F16

I/O

F17

I/O

E17

I/O

C18

I/O

F15

I/O

D17

LDC-I/O

E16

I/O

C17

I/O

B18

I/O

E15

HDC-I/O

A18

M2-I/O

A17

VCC

D16

M0-RTIG

B17

GND

D15

M1/RDATA

C16

I/O

B16

I/O

A16

I/O

D14

I/O

C15

I/O

B15

I/O

A15

I/O

C14

I/O

D13

I/O

B14

I/O

C13

I/O

B13

I/O

B12

I/O

D12

I/O

A12

I/O

B11

I/O

C11

I/O

A11

I/O

D11

I/O

A10

I/O

B10

I/O

C10

I/O

VCC

D10

GND

I/O

TCLKIN-I/O

PWRDN

GND

208

VCC

207

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed

outputs are default slew-rate limited.

In the PQ208 package, pins 15, 16, 64, 65, 90, 91, 142, 143, 170 and 195 are not connected.

*In PQ208, XC3090 and XC3195 have different pinouts.

2-150

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