XC3000FM Datasheet, PDF (44/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
XC3000 Families160-Pin PQFP Pinouts
XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts
PQFP
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
XC3064, XC3090,
XC3195
I/O*
I/O*
I/O_*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O_*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O_*
I/O_*
M1-RDATA
PQFP
Pin Number
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
XC3064, XC3090,
XC3195
GND
M0–RTRIG
VCC
M2-I/O
HDC-I/O
I/O
I/O
I/O
LDC-I/O
I/O_*
I/O_*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INIT-I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O_*
XTL2-I/O
GND
RESET
VCC
DONE/PG
PQFP
XC3064, XC3090,
Pin Number
XC3195
81
D7-I/O
82
XTL1-I/O-BCLKIN
83
I/O _*
84
I/O
85
I/O
86
D6-I/O
87
I/O
88
I/O
89
I/O
90
I/O
91
I/O
92
D5-I/O
93
CS0-I/O
94
I/O _*
95
I/O _*
96
I/O
97
I/O
98
D4-I/O
99
I/O
100
VCC
101
GND
102
D3-I/O
103
CS1-I/O
104
I/O
105
I/O
106
I/O_*
107
I/O _*
108
D2-I/O
109
I/O
110
I/O
111
I/O
112
I/O
113
I/O
114
D1-I/O
115
RDY/BUSY-RCLK-I/O
116
I/O
117
I/O
118
I/O _*
119
D0-DIN-I/O
120
DOUT-I/O
PQFP
Pin Number
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
XC3064, XC3090,
XC3195
CCLK
VCC
GND
A0-WS-I/O
A1-CS2-I/O
I/O
I/O
A2-I/O
A3-I/O
I/O
I/O
A15-I/O
A4-I/O
I/O
I/O
A14-I/O
A5-I/O
I/O _*
GND
VCC
A13-I/O
A6-I/O
I/O _*
I/O *
I/O
I/O
A12-I/O
A7-I/O
I/O
I/O
A11-I/O
A8-I/O
I/O
I/O
A10-I/O
A9-I/O
VCC
GND
PWRDWN
TCLKIN-I/O
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed
IOBs are default slew-rate limited.
*Indicates unconnected package pins (18) for the XC3064.
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