XC3000FM Datasheet, PDF (43/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000 Families 144-Pin Plastic TQFP Pinouts
XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
XC3042
XC3064
PWRDN
I/O-TCLKIN
I/O*
I/O
I/O
I/O*
I/O
I/O
I/O*
I/O
I/O
I/O
I/O
I/O
I/O*
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O*
I/O
I/O
I/O*
I/O*
I/O
I/O*
I/O
M1-RD
GND
MO-RT
VCC
M2-I/O
HDC-I/O
I/O
I/O
I/O
LDC-I/O
I/O*
I/O
I/O
Pin
Number
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
XC3042
XC3064
I/O
I/O*
I/O
I/O
INIT-I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O*
I/O*
I/O
I/O
I/O
I/O
XTL2(IN)-I/O
GND
RESET
VCC
DONE-PG
D7-I/O
XTL1(OUT)-BCLKIN-I/O
I/O
I/O
D6-I/O
I/O
I/O*
I/O
I/O
I/O*
D5-I/O
CS0-I/O
I/O*
I/O*
D4-I/O
I/O
VCC
GND
D3-I/O
CS1-I/O
I/O*
I/O*
D2-I/O
Pin
Number
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
XC3042
XC3064
I/O
I/O
I/O*
I/O
I/O*
D1-I/O
RDY/BUSY-RCLK-I/O
I/O
I/O
D0-DIN-I/O
DOUT-I/O
CCLK
VCC
GND
A0-WSI/O
A1-CS2-I/O
I/O
I/O
A2-I/O
A3-I/O
I/O
I/O
A15-I/O
A4-I/O
I/O*
I/O*
A14-I/O
A5-I/O
–
GND
VCC
A13-I/O
A6-I/O
I/O*
–
I/O*
A12-I/O
A7-I/O
I/O
I/O
A11-I/O
A8-I/O
I/O
I/O
A10-I/O
A9-I/O
VCC
GND
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed
outputs are default slew-rate limited.
* Indicates unconnected package pins (24) for the XC3042.
2-145